Datasheet

56F8355 Technical Data, Rev. 17

64 Freescale Semiconductor

Preliminary

Table 4-31 GPIOC Registers Address Map

(GPIOC_BASE = $00 F310)

GPIOC_PUR $0 Pullup Enable Register 0 x 07FF

GPIOC_DR $1 Data Register 0 x 0000

GPIOC_DDR $2 Data Direction Register 0 x 0000

GPIOC_PER $3 Peripheral Enable Register 0 x 07FF

GPIOC_IAR $4 Interrupt Assert Register 0 x 0000

GPIOC_IENR $5 Interrupt Enable Register 0 x 0000

GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOC_IPR $7 Interrupt Pending Register 0 x 0000

GPIOC_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOC_PPMODE $9 Push-Pull Mode Register 0 x 07FF

GPIOC_RAWDATA $A Raw Data Input Register —

Table 4-32 GPIOD Registers Address Map

(GPIOD_BASE = $00 F320)

GPIOD_PUR $0 Pullup Enable Register 0 x 1FFF

GPIOD_DR $1 Data Register 0 x 0000

GPIOD_DDR $2 Data Direction Register 0 x 0000

GPIOD_PER $3 Peripheral Enable Register 0 x 1FC0

GPIOD_IAR $4 Interrupt Assert Register 0 x 0000

GPIOD_IENR $5 Interrupt Enable Register 0 x 0000

GPIOD_IPOLR $6 Interrupt Polarity Register 0 x 0000

GPIOD_IPR $7 Interrupt Pending Register 0 x 0000

GPIOD_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000

GPIOD_PPMODE $9 Push-Pull Mode Register 0 x 1FFF

GPIOD_RAWDATA $A Raw Data Input Register —