Datasheet

Register Descriptions
56F8355 Technical Data, Rev. 17
Freescale Semiconductor 115
Preliminary
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1 Reserved—Bits 15–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2 GPIOC3 (C3)—Bit 3
This bit selects the alternate function for GPIOC3.
• 0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User Manual)
• 1 = SS1
6.5.8.3 GPIOC2 (C2)—Bit 2
This bit selects the alternate function for GPIOC2.
• 0 = INDEX1/TB2 (default)
•1 = MISO1
6.5.8.4 GPIOC1 (C1)—Bit 1
This bit selects the alternate function for GPIOC1.
• 0 = PHASEB1/TB1 (default)
•1 = MOSI1
SPI input 1 — 1 — See SPI controls for determining the direction
of each of the SPI pins.
SPI output 1 — 1 —
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits
is used for each pin.
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0 0 0
C3 C2 C1 C0
Write
RESET
000000000000 0 0 0 0
Table 6-2 Control of Pads Using SIM_GPS Control
1
(Continued)
Pin Function
Control Registers
Comments
GPIOC_PER GPIOC_DTR
SIM_GPS
Quad Timer
SCR Register
OEN bits