Datasheet

56F8355 Technical Data, Rev. 17
116 Freescale Semiconductor
Preliminary
6.5.8.5 GPIOC0 (C0)—Bit 0
This bit selects the alternate function for GPIOC0.
• 0 = PHASEA1/TB0 (default)
• 1 = SCLK1
6.5.9 Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used enable or disable clocks to the peripherals as a power savings
feature. The clocks can be individually controlled for each peripheral on the chip.
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
6.5.9.1 External Memory Interface Enable (EMI)—Bit 15
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.2 Analog-to-Digital Converter B Enable (ADCB)—Bit 14
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3 Analog-to-Digital Converter A Enable (ADCA)—Bit 13
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4 FlexCAN Enable (CAN)—Bit 12
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.5 Decoder 1 Enable (DEC1)—Bit 11
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
Base + $C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0 SPI 1 SPI 0 PWMB PWMA
Write
RESET
11 111 1 1 1 1 1 11 1 1 1 1