Datasheet

Architecture Block Diagram
56F8355 Technical Data, Rev. 17
Freescale Semiconductor 13
Preliminary
Figure 1-2 Peripheral Subsystem
IPBus
Timer A
Timer C
Timer D
SPI 1
ADCB
ADCA
FlexCAN
GPIO A
SPI 0
SCI 0
SCI 1
Interrupt
Controller
To/From IPBus Bridge
PWMA
PWMB
RESET
Quadrature Decoder 0
Note: ADC A and ADC B use the same volt-
age reference circuit with V
REFH
, V
REFP
V
REFMID
, V
REFN
, and V
REFLO
pins.
GPIO B
GPIO C
GPIO D
GPIO E
GPIO F
Timer B
Quadrature Decoder 1
CLKGEN
(OSC/PLL)
POR & LVI
SIM
SYNC Output
SYNC Output
TEMP_SENSE
NOT available on the 56F8155 device.
COP
ch3i
ch2i
ch3o
ch2o
1
4
8
8
2
2
2
2
4
13
13
4
4
Low-Voltage Interrupt
System POR
COP Reset