Datasheet

56F8355 Technical Data, Rev. 17
142 Freescale Semiconductor
Preliminary
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Figure 10-5 Asynchronous Reset Timing
Bias Current, high-drive mode I
BIASH
—250290μA
Bias Current, low-drive mode I
BIASL
—80110μA
Quiescent Current, power-down mode I
PD
—0 1μA
Table 10-16 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol
Typical
Min
Typical
Max
Unit See Figure
Minimum RESET
Assertion Duration t
RA
16T — ns 10-5
Edge-sensitive Interrupt Request Width t
IRW
1.5T — ns 10-6
IRQA, IRQB Assertion to General Purpose
Output Valid, caused by first instruction
execution in the interrupt service routine
t
IG
18T — ns 10-7
t
IG
- FAST 14T —
IRQA Width Assertion to Recover from Stop
State
3
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
t
IW
1.5T — ns 10-9
Table 10-15 Crystal Oscillator Parameters
Characteristic Symbol Min Typ Max Unit
First Fetch
t
RA
t
RAZ
t
RDA
A0–A15,
D0–D15
RESET