Datasheet

Register Descriptions
56F8355 Technical Data, Rev. 17
Freescale Semiconductor 85
Preliminary
5.6.5.4 Reserved—Bits 9–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.6 Interrupt Priority Register 5 (IPR5)
Figure 5-8 Interrupt Priority Register 5 (IPR5)
Base + $5
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
DEC1_XIRQ
IPL
DEC1_HIRQ
IPL
SCI1_RCV
IPL
SCI1_RERR
IPL
0 0
SCI1_TIDL
IPL
SCI1_XMIT
IPL
SPI0_XMIT
IPL
Write
RESET
000000 0 000000000