Datasheet

Architecture Block Diagram

56F8356 Technical Data, Rev. 13

Freescale Semiconductor 11

Preliminary

Figure 1-1 System Bus Interfaces

Note: Flash memories are encapsulated within the Flash Module(FM). Flash control is accomplished by the

I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the

Flash memories.

Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits.

56800E

Program

Flash

Program

RAM

Data RAM

EMI

Data Flash

IPBus

Bridge

Boot

Flash

Module

CHIP

TAP

Controller

TAP

Linking

NOT available on the 56F8156 device.

JTAG / EOnCE

External

JTAG

Port

pdb_m[15:0]

pab[20:0]

cdbw[31:0]

xab1[23:0]

xab2[23:0]

xdb2_m[15:0]

cdbr_m[31:0]

Address

Control

Data

To Flash

Control Logic

IPBus