Datasheet

56F8356 Technical Data, Rev. 13
122 Freescale Semiconductor
Preliminary
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.6 Decoder 0 Enable (DEC0)—Bit 10
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.7 Quad Timer D Enable (TMRD)—Bit 9
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.8 Quad Timer C Enable (TMRC)—Bit 8
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.9 Quad Timer B Enable (TMRB)—Bit 7
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.10 Quad Timer A Enable (TMRA)—Bit 6
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.11 Serial Communications Interface 1 Enable (SCI1)—Bit 5
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled