Datasheet

56F8356 Technical Data, Rev. 13
148 Freescale Semiconductor
Preliminary
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler
clock and prescaler set to ÷ 1), the EMI quadrature clock is generated using both edges of the EXTAL
clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL.
DCAOE and DCAEO are used to make this duty cycle adjustment where needed.
DCAOE and DCAEO are calculated as follows:
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of Table 10-16 to make the appropriate selection.
Figure 10-4 External Memory Interface Timing
DCAOE =
=
0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1
0.0 all other cases
DCAEO =
=
MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to
÷ 1
0.0 all other cases
Example of DCAOE and DCAEO calculation
Assuming prescaler is set for
÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high:
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
t
DRD
t
RDD
t
AD
t
DOH
t
DOS
t
DWR
t
RDWR
t
WAC
t
WRRD
t
WR
t
AWR
t
WRWR
t
ARDD
t
RDA
t
RDRD
t
RD
t
ARDA
Data Out Data In
A0-Axx,CS
RD
WR
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.