Datasheet

External Memory Interface Timing
56F8356 Technical Data, Rev. 13
Freescale Semiconductor 149
Preliminary
Note: When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
Table 10-16 External Memory Interface Timing
Characteristic Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit
Address Valid to WR Asserted
t
AWR
WWS=0 -1.477 0.50
WWSS
ns
WWS>0 -1.564 0.75 + DCAOE
WR
Width Asserted to WR
Deasserted
t
WR
WWS=0 -0.186 0.25 + DCAOE
WWS
ns
WWS>0 -0.256 0
Data Out Valid to WR
Asserted
t
DWR
WWS=0 -9.568 0.25 + DCAEO
WWSS
ns
WWS=0 -1.721 0.00
WWS>0 -9.227 0.50
WWS>0 -1.808 0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
t
DOH
-2.287 0.25 + DCAEO WWSH
ns
Valid Data Out Set-Up Time to
WR Deasserted
t
DOS
-1.622 0.25 + DCAOE
WWS,WWSS
ns
-9.041 0.50
Valid Address after WR
Deasserted
t
WAC
-3.918 0.25 + DCAEO WWSH
ns
RD Deasserted to Address
Invalid
t
RDA
-2.229 0.00 RWSH
ns
Address Valid to RD Deasserted
t
ARDD
-1.887 1.00 RWSS,RWS
ns
Valid Input Data Hold after RD
Deasserted
t
DRD
0.00
N/A
1
—
ns
RD Assertion Width
t
RD
0.212 1.00 RWS
ns
Address Valid to Input Data
Valid
t
AD
-14.427 1.00
RWSS,RWS
ns
-19.751 1.25 + DCAOE
Address Valid to RD
Asserted
t
ARDA
-2.121 0.00 RWSS ns
RD
Asserted to Input Data Valid
t
RDD
-12.306 1.00
RWSS,RWS
ns
-17.630 1.25 + DCAOE
WR
Deasserted to RD Asserted
t
WRRD
-1.923 0.25 + DCAEO
WWSH,RWSS
ns