Datasheet

56F8356 Technical Data, Rev. 13
150 Freescale Semiconductor
Preliminary
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
RD Deasserted to RD Asserted
t
RDRD
-0.234
2
0.00
RWSS,RWSH
MDAR
3
,
4
ns
WR
Deasserted to WR Asserted
t
WRWR
WWS=0 -1.279 0.75 + DCAEO
WWSS, WWSH ns
WWS>0 -0.938 1.00
RD
Deasserted to WR Asserted
t
RDWR
WWS=0 -0.046 0.50
RWSH, WWSS,
MDAR
3
ns
WWS>0 0.052 0.75 + DCAOE
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is acive in this calculation only when the chip select changes.
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
Characteristic Symbol
Typical
Min
Typical
Max
Unit See Figure
RESET
Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—21ns10-5
Minimum RESET
Assertion Duration t
RA
16T — ns 10-5
RESET
Deassertion to First External Address
Output
3
t
RDA
63T 64T ns 10-5
Edge-sensitive Interrupt Request Width t
IRW
1.5T — ns 10-6
IRQA
, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
t
IDM
18T — ns 10-7
t
IDM - FAST
14T —
IRQA
, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
18T — ns 10-7
t
IG - FAST
14T —
Delay from IRQA
Assertion (exiting Wait) to
External Data Memory Access
4
t
IRI
22T — ns 10-8
t
IRI -FAST
18T —
Delay from IRQA
Assertion to External Data
Memory Access (exiting Stop)
t
IF
22T — ns 10-9
t
IF - FAST
18T —
Table 10-16 External Memory Interface Timing (Continued)
Characteristic Symbol
Wait States
Configuration
DM
Wait States
Controls
Unit