Datasheet

Reset, Stop, Wait, Mode Select, and Interrupt Timing

56F8356 Technical Data, Rev. 13

Freescale Semiconductor 151

Preliminary

Figure 10-5 Asynchronous Reset Timing

Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive)

IRQA Width Assertion to Recover from Stop

State

1.5T — ns 10-9

1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and

Stop modes), T = 125ns.

2. Parameters listed are guaranteed by design.

3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2

4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.

This is not the minimum required so that the IRQA

interrupt is accepted.

5. The interrupt instruction fetch is visible on the pins only in Mode 3.

Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing

1,2

(Continued)

Characteristic Symbol

Typical

Min

Typical

Max

Unit See Figure

First Fetch

RAZ

RDA

A0–A15,

D0–D15

RESET

IRQA,

IRQB

IRW