56F8356 Technical Data, Rev. 13
156 Freescale Semiconductor
Preliminary
Figure 10-12 SPI Slave Timing (CPHA = 0)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
t
C
t
CL
t
CL
t
F
t
CH
t
DI
MSB in Bits 14–1 LSB in
SS
(Input)
t
CH
t
DH
t
R
t
ELG
t
ELD
t
F
Slave LSB out
t
D
t
A
t
DS
t
DV
t
R
t
DI
