Datasheet

56F8356 Technical Data, Rev. 13
18 Freescale Semiconductor
Preliminary
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 144-Pin LQFP
Signal Name Pin No. Type
State
During
Reset
Signal Description
V
DD_IO
1 Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage
regulator, if it is enabled.
V
DD_IO
16
V
DD_IO
31
V
DD_IO
38
V
DD_IO
66
V
DD_IO
84
V
DD_IO
119
V
DDA_ADC
102 Supply ADC Power — This pin supplies 3.3V power to the ADC modules.
It must be connected to a clean analog power supply.
V
DDA_OSC_PLL
80 Supply Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power
supply.
V
SS
27 Supply V
SS
— These pins provide ground for chip logic and I/O drivers.
V
SS
37
V
SS
63
V
SS
69
V
SS
144
V
SSA_ADC
103 Supply ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.