Datasheet

Signal Pins
56F8356 Technical Data, Rev. 13
Freescale Semiconductor 29
Preliminary
SCLK0
(GPIOE4)
130 Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input.
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCLK0.
To deactivate the internal pull-up resistor, clear bit 4 in the
GPIOE_PUR register.
MOSI0
(GPIOE5)
132 Input/
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
SPI 0 Master Out/Slave In — This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge
the slave device uses to latch the data.
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MOSI0.
To deactivate the internal pull-up resistor, clear bit 5 in the
GPIOE_PUR register.
MISO0
(GPIOE6)
131 Input/
Output
Input/
Output
Input,
pull-up
enabled
SPI 0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of
a slave device is placed in the high-impedance state if the slave
device is not selected. The slave device places data on the MISO
line a half-cycle before the clock edge the master device uses to
latch the data.
Port E GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MISO0.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOE_PUR register.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued)
Signal Name Pin No. Type
State
During
Reset
Signal Description