Datasheet

56F8356 Technical Data, Rev. 13

52 Freescale Semiconductor

Preliminary

CSOR 0 $8 Chip Select Option Register 0 0x5FCB programmed for chip

select for program space, word

wide, read and write, 11 waits

CSOR 1 $9 Chip Select Option Register 1 0x5FAB programmed for chip

select for data space, word

wide, read and write, 11 waits

CSOR 2 $A Chip Select Option Register 2

CSOR 3 $B Chip Select Option Register 3

CSOR 4 $C Chip Select Option Register 4

CSOR 5 $D Chip Select Option Register 5

CSOR 6 $E Chip Select Option Register 6

CSOR 7 $F Chip Select Option Register 7

CSTC 0 $10 Chip Select Timing Control Register 0

CSTC 1 $11 Chip Select Timing Control Register 1

CSTC 2 $12 Chip Select Timing Control Register 2

CSTC 3 $13 Chip Select Timing Control Register 3

CSTC 4 $14 Chip Select Timing Control Register 4

CSTC 5 $15 Chip Select Timing Control Register 5

CSTC 6 $16 Chip Select Timing Control Register 6

CSTC 7 $17 Chip Select Timing Control Register 7

BCR $18 Bus Control Register 0x016B sets the default

number of wait states to 11 for

both read and write accesses

Table 4-11 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F040)

TMRA0_CMP1 $0 Compare Register 1

TMRA0_CMP2 $1 Compare Register 2

TMRA0_CAP $2 Capture Register

TMRA0_LOAD $3 Load Register

TMRA0_HOLD $4 Hold Register

TMRA0_CNTR $5 Counter Register

TMRA0_CTRL $6 Control Register

Table 4-10 External Memory Integration Registers Address Map (Continued)

(EMI_BASE = $00 F020)