Datasheet

56F8356 Technical Data, Rev. 13
64 Freescale Semiconductor
Preliminary
ADCA_OFS 0 $21 Offset Register 0
ADCA_OFS 1 $22 Offset Register 1
ADCA_OFS 2 $23 Offset Register 2
ADCA_OFS 3 $24 Offset Register 3
ADCA_OFS 4 $25 Offset Register 4
ADCA_OFS 5 $26 Offset Register 5
ADCA_OFS 6 $27 Offset Register 6
ADCA_OFS 7 $28 Offset Register 7
ADCA_POWER $29 Power Control Register
ADCA_CAL $2A ADC Calibration Register
Table 4-21 Analog-to-Digital Converter Registers Address Map
(ADCB_BASE = $00 F240)
Register Acronym Address Offset Register Description
ADCB_CR 1 $0 Control Register 1
ADCB_CR 2 $1 Control Register 2
ADCB_ZCC $2 Zero Crossing Control Register
ADCB_LST 1 $3 Channel List Register 1
ADCB_LST 2 $4 Channel List Register 2
ADCB_SDIS $5 Sample Disable Register
ADCB_STAT $6 Status Register
ADCB_LSTAT $7 Limit Status Register
ADCB_ZCSTAT $8 Zero Crossing Status Register
ADCB_RSLT 0 $9 Result Register 0
ADCB_RSLT 1 $A Result Register 1
ADCB_RSLT 2 $B Result Register 2
ADCB_RSLT 3 $C Result Register 3
ADCB_RSLT 4 $D Result Register 4
ADCB_RSLT 5 $E Result Register 5
ADCB_RSLT 6 $F Result Register 6
ADCB_RSLT 7 $10 Result Register 7
ADCB_LLMT 0 $11 Low Limit Register 0
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym Address Offset Register Description