Datasheet

Peripheral Memory Mapped Registers

56F8356 Technical Data, Rev. 13

Freescale Semiconductor 67

Preliminary

Table 4-26 Serial Peripheral Interface 1 Registers Address Map

(SPI1_BASE = $00 F2B0)

SPI1_SPSCR $0 Status and Control Register

SPI1_SPDSR $1 Data Size Register

SPI1_SPDRR $2 Data Receive Register

SPI1_SPDTR $3 Data Transmitter Register

Table 4-27 Computer Operating Properly Registers Address Map

(COP_BASE = $00 F2C0)

COPCTL $0 Control Register

COPTO $1 Time Out Register

COPCTR $2 Counter Register

Table 4-28 Clock Generation Module Registers Address Map

(CLKGEN_BASE = $00 F2D0)

PLLCR $0 Control Register

PLLDB $1 Divide-By Register

PLLSR $2 Status Register

Reserved

SHUTDOWN $4 Shutdown Register

OSCTL $5 Oscillator Control Register

Table 4-29 GPIOA Registers Address Map

(GPIOA_BASE = $00 F2E0)

Address Offset Register Description Reset Value

GPIOA_PUR

$0 Pull-up Enable Register

0 x 3FFF

GPIOA_DR

$1 Data Register

0 x 0000

GPIOA_DDR

$2 Data Direction Register

0 x 0000

GPIOA_PER

$3 Peripheral Enable Register

0 x 3FFF

GPIOA_IAR

$4 Interrupt Assert Register

0 x 0000