Datasheet

Peripheral Memory Mapped Registers

56F8356 Technical Data, Rev. 13

Freescale Semiconductor 71

Preliminary

Table 4-35 System Integration Module Registers Address Map

(SIM_BASE = $00 F350)

SIM_CONTROL $0 Control Register

SIM_RSTSTS $1 Reset Status Register

SIM_SCR0 $2 Software Control Register 0

SIM_SCR1 $3 Software Control Register 1

SIM_SCR2 $4 Software Control Register 2

SIM_SCR3 $5 Software Control Register 3

SIM_MSH_ID $6 Most Significant Half JTAG ID

SIM_LSH_ID $7 Least Significant Half JTAG ID

SIM_PUDR $8 Pull-up Disable Register

Reserved

SIM_CLKOSR $A Clock Out Select Register

SIM_GPS $B Quad Decoder 1 / Timer B / SPI 1 Select Register

SIM_PCE $C Peripheral Clock Enable Register

SIM_ISALH $D I/O Short Address Location High Register

SIM_ISALL $E I/O Short Address Location Low Register

Table 4-36 Power Supervisor Registers Address Map

(LVI_BASE = $00 F360)

LVI_CONTROL $0 Control Register

LVI_STATUS $1 Status Register

Table 4-37 Flash Module Registers Address Map

(FM_BASE = $00 F400)

FMCLKD $0 Clock Divider Register

FMMCR $1 Module Control Register

Reserved

FMSECH $3 Security High Half Register

FMSECL $4 Security Low Half Register