Datasheet

56F8356 Technical Data, Rev. 13
94 Freescale Semiconductor
Preliminary
5.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.7.6 Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.7 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level
(DEC0_XIRQ IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.7.8 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2