56F8356/56F8156 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.
Document Revision History Version History Description of Change Rev 1.0 Initial Public Release Rev 2.0 Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added “Typical Min” values to Table 10-18. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing Table 10-18, ADC Parameters Table 10-24, and IO Loading Coefficients at 10MHz Table 10-25.
56F8356/56F8156 General Description Note: Features in italics are NOT available in the 56F8156 device.
Table of Contents Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 1.2 1.3 1.4 1.5 1.6 56F8356/56F8156 Features . . . . . . . . . . . .5 Device Description. . . . . . . . . . . . . . . . . . . .7 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . .9 Architecture Block Diagram . . . . . . . . . . . .10 Product Documentation . . . . . . . . . . . . . . .14 Data Sheet Conventions . . . . . . . . . . . . . .14 7.2 Flash Access Blocking Mechanisms . . . .
6F8356/56F8156 Features Part 1 Overview 1.1 56F8356/56F8156 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
1.1.3 Memory Note: Features in italics ae NOT available in the 56F8156 device.
Device Description • • Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8356, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B — In the 56F8156, SPI1 can alternately be used only as GPIO • • • • • • • • 1.1.
1.2.1 56F8356 Features The 56F8356 controller includes 256KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. It also supports program execution from external memory. A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas.
Award-Winning Development Environment A key application-specific feature of the 56F8156 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control.
1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8156 device and are shaded in the following figures. The 56F8356/56F8156 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories, the external memory interface and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function.
Architecture Block Diagram 5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw[31:0] Program RAM 56800E 17 CHIP TAP Controller EMI 16 6 Address Data Control TAP Linking xab1[23:0] xab2[23:0] External JTAG Port Data RAM Data Flash cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge To Flash Control Logic Flash Module NOT available on the 56F8156 device. IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Module(FM).
To/From IPBus Bridge Interrupt Controller CLKGEN (OSC/PLL) Low Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 RESET SIM 2 Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 SPI 1 12 PWMA SYNC Output GPIOA 13 PWMB GPIOB SYNC Output GPIOC ch2i ch3i 1 Timer C GPIOD ch2o ch3o GPIOE GPIOF 4 2 ADCB SPI0 8 ADCA SCI0 TEMP_SENSE 2 8 1 SCI1 NOT available on the 56F8156 device.
Architecture Block Diagram Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
1.5 Product Documentation The documents in Table 1-3 are required for a complete description and proper design with the 56F8356/56F8156 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com.
Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8356 and 56F8156 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS Other Supply Ports PLL and Clock VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO A0 - A5 (GPIOA8 - 13) External Address Bus or GPIO External Data Bus or GPIO A6 - A7 (GPIOE2 - 3) A8 - A15 (GPIOA0 - 7) GPIOB0 (A16) D0 - D6 (GPIOF9 - 15) D7 - D15 (GPIOF0 - 8) RD External Bus Control or GPIO WR PS / CS0 (GPIOD8) DS / CS1 (GPIOD9) GPIOD0 - 1 (CS2 - 3) 7 1 1 1 1 1 5 1 1 1 4 2 1 1 1 1 56F8356 1 1 1 1 1 1 1
Introduction Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS VCAP1 - VCAP4 Other Supply Ports VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO PLL and Clock A0 - A5 (GPIOA8 - 13) External Address Bus or GPIO External Data Bus or GPIO A6 - A7 (GPIOE2 - 3) A8 - A15 (GPIOA0 - 7) GPIOB0 (A16) D0 - D6 (GPIOF9 - 15) D7 - D15 (GPIOF0 - 8) RD External Bus Control or GPIO WR PS / CS0 (GPIOD8) DS / CS1 (GPIOD9) GPIOD0 - 1 (CS2 - 3) SCI 0 or GPIO TXD0 (GPIOE0) RXD0 (GPIOE1) S
2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin shows that it is tri-stated during reset.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type State During Reset OCR_DIS 79 Input Input Signal Description On-Chip Regulator Disable — Tie this pin to VSS to enable the on-chip regulator Tie this pin to VDD to disable the on-chip regulator This pin is intended to be a static DC signal from power-up to shut down. Do not try to toggle this pin for power savings during operation.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type A0 138 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Address Bus — A0 - A5 specify six of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0 - A5 and EMI control signals are tri-stated when the external bus is inactive.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type A8 19 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Address Bus— A8 - A15 specify eight of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A8 - A15 and EMI control signals are tri-stated when the external bus is inactive.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type State During Reset GPIOB0 33 Schmitt Input/ Output Input, pull-up enabled (A16) Output Signal Description Port B GPIO — This GPIO pin can be programmed as an input or output pin. Address Bus — A16 specifies one of the address lines for external program or data memory accesses.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type D7 28 Input/ Output (GPIOF0) State During Reset In reset, output is disabled, pull-up is enabled Input/ Output D8 (GPIOF1) 29 D9 (GPIOF2) 30 D10 (GPIOF3) 32 D11 (GPIOF4) 133 D12 (GPIOF5) 134 D13 (GPIOF6) 135 D14 (GPIOF7) 136 D15 137 Signal Description Data Bus — D7 - D14 specify part of the data for external program or data memory accesses.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type RD 45 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Read Enable — RD is asserted during external memory read cycles. When RD is asserted low, pins D0 - D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted high, the external data is latched inside the device.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type DS 47 Output (CS1) State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Memory Select — This signal is actually CS1 in the EMI, which is programmed at reset for compatibility with the 56F80x DS signal. DS is asserted low for external data memory access.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type RXD0 5 Input (GPIOE1) Input/ Output State During Reset Input, pull-up enabled Signal Description Receive Data — SCI0 receive data input Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOE_PUR register.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State During Reset Signal Name Pin No. Type Signal Description TDO 124 Output In reset, output is disabled, pull-up is enabled Test Data Output — This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type PHASEB0 140 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase B — Quadrature Decoder 0, PHASEB input (TA1) Schmitt Input/ Output TA1 — Timer A, Channel (GPIOC5) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEB0.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type State During Reset Signal Description SCLK0 130 Schmitt Input/ Output Input, pull-up enabled SPI 0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. (GPIOE4) Schmitt Input/ Output Port E GPIO — This GPIO pin can be individually programmed as an input or output pin.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type SS0 129 Input (GPIOE7) State During Reset Input, pull-up enabled Input/ Output Signal Description SPI 0 Slave Select — SS0 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Port E GPIO — This GPIO pin can be individually programmed as input or output pin. After reset, the default state is SS0.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type PHASEB1 7 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase B1 — Quadrature Decoder 1, PHASEB input for decoder 1. (TB1) Schmitt Input/ Output TB1 — Timer B, Channel 1 (MOSI1) Schmitt Input/ Output SPI 1 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type INDEX1 8 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index1 — Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output TB2 — Timer B, Channel 2 (MISO1) Schmitt Input/ Output SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State During Reset Signal Name Pin No. Type PWMA0 62 Output PWMA0 - 5 — These are six PWMA outputs. PWMA1 64 PWMA2 65 In reset, output is disabled, pull-up is enabled PWMA3 67 PWMA4 68 PWMA5 70 ISA0 113 Schmitt Input Input, pull-up enabled ISA0 - 2 — These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) State During Reset Signal Name Pin No.
Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type State During Reset TD0 116 Schmitt Input/ Output Input, pull-up enabled (GPIOE10) TD1 (GPIOE11) 117 Schmitt Input/ Output Signal Description TD0 - 1 — Timer D, Channels 0 and 1 Port E GPIO — These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to Timer functionality.
Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type EXTBOOT 112 Schmitt Input State During Reset Input, pull-up enabled Signal Description External Boot — This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4.
Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference from the OCCS chapter of the 56F8300 Peripheral User Manual.
External Clock Operation parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 3 Terminal 2 Terminal EXTAL XTAL EXTAL Rz CL1 XTAL Rz Sample External Ceramic Resonator Parameters: Rz = 750 KΩ CLKMODE = 0 CL2 C1 C2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 Peripheral User Manual. 3.2.
Introduction This section provides memory maps for: • • Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 4-1. Note: Data Flash and Program RAM are NOT available on the 56F8156 device.
Table 4-1 Chip Memory Configurations On-Chip Memory 56F8356 56F8156 Use Restrictions Data RAM 16KB 16KB None Program Boot Flash 16KB 16KB Erase / Program via Flash Interface unit and word to CDBW 4.2 Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory map configurations that are possible at reset.
Interrupt Vector Table accessed using a 16-bit 56800-compatible address bus. To address this situation, the EMI_MODE pin can be used to configure four GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable in the 56F8356/56F8156). The EMI_MODE pin also affects the reset vector address, as provided in Table 4-4. Additional pins must be configured as address or chip select signals to access addresses at P:$10 0000 and above. Note: Program RAM is NOT available on the 56F8156 device.
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part 5.6.
Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + PLL 21 0-2 P:$2A PLL FM 22 0-2 P:$2C FM Access Error Interrupt FM 23 0-2 P:$2E FM Command Complete FM 24 0-2 P:$30 FM Command, data and address Buffers Empty Peripheral Interrupt Function Reserved FLEXCAN 26 0-2 P:$34 FLEXCAN Bus Off FLEXCAN 27 0-2 P:$36 FLEXCAN Error FLEXCAN 28 0-2 P:$38 FLEXCAN Wake Up FLEXCAN 29 0-2 P:$3A FLEXCAN Mes
Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + TMRD 52 0-2 P:$68 Timer D, Channel 0 TMRD 53 0-2 P:$6A Timer D, Channel 1 TMRD 54 0-2 P:$6C Timer D, Channel 2 TMRD 55 0-2 P:$6E Timer D, Channel 3 TMRC 56 0-2 P:$70 Timer C, Channel 0 TMRC 57 0-2 P:$72 Timer C, Channel 1 TMRC 58 0-2 P:$74 Timer C, Channel 2 TMRC 59 0-2 P:$76 Timer C, Channel 3 TMRB 60 0-2 P:$78 Timer B, Channel 0 TMRB 61 0-2 P:$7A Tim
Data Map 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip reset addresses; therefore, these locations are not interrupt vectors. 2. 4.4 Data Map Note: Data Flash is NOT available on the 56F8156 device.
on the Data Memory buses and is controlled separately by its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash Controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset.
EOnCE Memory Map 4.
4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-9 summarizes base addresses for the set of peripherals on the 56F8356 and 56F8156 devices. Peripherals are listed in order of the base address.
Peripheral Memory Mapped Registers Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number GPIO Port E GPIOE X:$00 F330 4-33 GPIO Port F GPIOF X:$00 F340 4-34 SIM SIM X:$00 F350 4-35 Power Supervisor LVI X:$00 F360 4-36 FM FM X:$00 F400 4-37 FlexCAN FC X:$00 F800 4-38 Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Register Acronym CSBAR 0 Address Offset $0 Register Description Chip Se
Table 4-10 External Memory Integration Registers Address Map (Continued) (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description Reset Value CSOR 0 $8 Chip Select Option Register 0 0x5FCB programmed for chip select for program space, word wide, read and write, 11 waits CSOR 1 $9 Chip Select Option Register 1 0x5FAB programmed for chip select for data space, word wide, read and write, 11 waits CSOR 2 $A Chip Select Option Register 2 CSOR 3 $B Chip Select Option Register 3
Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_SCR $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and Control Register Reserve TMRA1_CMP1 $10 Compare Register 1 TMRA1_CMP2 $11 Compare Register 2 TMRA1_CAP $12 Capture Register TMRA1_LOAD $13 Load Registe
Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL $36 Control Register TMRA3_SCR $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_COMSC $3A Comparator Status and Control Register Table 4-12 Quad Timer B Registers Address Ma
Peripheral Memory Mapped Registers Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8156 device Register Acronym Address Offset Register Description TMRB1_SCR $17 Status and Control Register TMRB1_CMPLD1 $18 Comparator Load Register 1 TMRB1_CMPLD2 $19 Comparator Load Register 2 TMRB1_COMSCR $1A Comparator Status and Control Register Reserved TMRB2_CMP1 $20 Compare Register 1 TMRB2_CMP2 $21 Compare Register 2 TMRB2_
Table 4-13 Quad Timer C Registers Address Map (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC0_CMP1 $0 Compare Register 1 TMRC0_CMP2 $1 Compare Register 2 TMRC0_CAP $2 Capture Register TMRC0_LOAD $3 Load Register TMRC0_HOLD $4 Hold Register TMRC0_CNTR $5 Counter Register TMRC0_CTRL $6 Control Register TMRC0_SCR $7 Status and Control Register TMRC0_CMPLD1 $8 Comparator Load Register 1 TMRC0_CMPLD2 $9 Comparator Load Register 2 TMRC0_COMSCR $A
Peripheral Memory Mapped Registers Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC2_SCR $27 Status and Control Register TMRC2_CMPLD1 $28 Comparator Load Register 1 TMRC2_CMPLD2 $29 Comparator Load Register 2 TMRC2_COMSCR $2A Comparator Status and Control Register Reserved TMRC3_CMP1 $30 Compare Register 1 TMRC3_CMP2 $31 Compare Register 2 TMRC3_CAP $32 Capture Register TMRC3_LOAD $33 Load Re
Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8156 device Register Acronym Address Offset Register Description Reserved TMRD1_CMP1 $10 Compare Register 1 TMRD1_CMP2 $11 Compare Register 2 TMRD1_CAP $12 Capture Register TMRD1_LOAD $13 Load Register TMRD1_HOLD $14 Hold Register TMRD1_CNTR $15 Counter Register TMRD1_CTRL $16 Control Register TMRD1_SCR $17 Status and Control Register TMRD1_CMPLD1 $18 Comparat
Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8156 device Register Acronym Address Offset Register Description TMRD3_CTRL $36 Control Register TMRD3_SCR $37 Status and Control Register TMRD3_CMPLD1 $38 Comparator Load Register 1 TMRD3_CMPLD2 $39 Comparator Load Register 2 TMRD3_COMSCR $3A Comparator Status and Control Register Table 4-15 Pulse Width Modulator A Registers Address M
Table 4-16 Pulse Width Modulator B Registers Address Map (PWMB_BASE = $00 F160) Register Acronym Address Offset Register Description PWMB_PMCTL $0 Control Register PWMB_PMFCTL $1 Fault Control Register PWMB_PMFSA $2 Fault Status Acknowledge Register PWMB_PMOUT $3 Output Control Register PWMB_PMCNT $4 Counter Register PWMB_PWMCM $5 Counter Modulo Register PWMB_PWMVAL0 $6 Value Register 0 PWMB_PWMVAL1 $7 Value Register 1 PWMB_PWMVAL2 $8 Value Register 2 PWMB_PWMVAL3 $9 Value Re
Peripheral Memory Mapped Registers Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued) (DEC0_BASE = $00 F180) Register Acronym Address Offset Register Description DEC0_POSDH $4 Position Difference Counter Hold Register DEC0_REV $5 Revolution Counter Register DEC0_REVH $6 Revolution Hold Register DEC0_UPOS $7 Upper Position Counter Register DEC0_LPOS $8 Lower Position Counter Register DEC0_UPOSH $9 Upper Position Hold Register DEC0_LPOSH $A Lower Position Hold Register
Table 4-19 Interrupt Control Registers Address Map (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description IPR 0 $0 Interrupt Priority Register 0 IPR 1 $1 Interrupt Priority Register 1 IPR 2 $2 Interrupt Priority Register 2 IPR 3 $3 Interrupt Priority Register 3 IPR 4 $4 Interrupt Priority Register 4 IPR 5 $5 Interrupt Priority Register 5 IPR 6 $6 Interrupt Priority Register 6 IPR 7 $7 Interrupt Priority Register 7 IPR 8 $8 Interrupt Priority Register 8 IPR
Peripheral Memory Mapped Registers Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_CR 2 $1 Control Register 2 ADCA_ZCC $2 Zero Crossing Control Register ADCA_LST 1 $3 Channel List Register 1 ADCA_LST 2 $4 Channel List Register 2 ADCA_SDIS $5 Sample Disable Register ADCA_STAT $6 Status Register ADCA_LSTAT $7 Limit Status Register ADCA_ZCSTAT $8 Zero Crossing Status Register AD
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_OFS 0 $21 Offset Register 0 ADCA_OFS 1 $22 Offset Register 1 ADCA_OFS 2 $23 Offset Register 2 ADCA_OFS 3 $24 Offset Register 3 ADCA_OFS 4 $25 Offset Register 4 ADCA_OFS 5 $26 Offset Register 5 ADCA_OFS 6 $27 Offset Register 6 ADCA_OFS 7 $28 Offset Register 7 ADCA_POWER $29 Power Control Register ADCA_CAL $2A ADC Calibration
Peripheral Memory Mapped Registers Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_LLMT 1 $12 Low Limit Register 1 ADCB_LLMT 2 $13 Low Limit Register 2 ADCB_LLMT 3 $14 Low Limit Register 3 ADCB_LLMT 4 $15 Low Limit Register 4 ADCB_LLMT 5 $16 Low Limit Register 5 ADCB_LLMT 6 $17 Low Limit Register 6 ADCB_LLMT 7 $18 Low Limit Register 7 ADCB_HLMT 0 $19 High Limit Register 0 ADC
Table 4-23 Serial Communication Interface 0 Registers Address Map (SCI0_BASE = $00 F280) Register Acronym Address Offset Register Description SCI0_SCIBR $0 Baud Rate Register SCI0_SCICR $1 Control Register Reserved SCI0_SCISR $3 Status Register SCI0_SCIDR $4 Data Register Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym Address Offset Register Description SCI1_SCIBR $0 Baud Rate Register SCI1_SCICR $1 Control Register Reserved
Peripheral Memory Mapped Registers Table 4-26 Serial Peripheral Interface 1 Registers Address Map (SPI1_BASE = $00 F2B0) Register Acronym Address Offset Register Description SPI1_SPSCR $0 Status and Control Register SPI1_SPDSR $1 Data Size Register SPI1_SPDRR $2 Data Receive Register SPI1_SPDTR $3 Data Transmitter Register Table 4-27 Computer Operating Properly Registers Address Map (COP_BASE = $00 F2C0) Register Acronym Address Offset Register Description COPCTL $0 Control Register CO
Table 4-29 GPIOA Registers Address Map (Continued) (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_IENR $5 Interrupt Enable Register 0 x 0000 GPIOA_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOA_IPR $7 Interrupt Pending Register 0 x 0000 GPIOA_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOA_RAWDATA $A Raw Data Input Register — Table 4-30 GPIOB Registers Address Map (GPIOB
Peripheral Memory Mapped Registers Table 4-31 GPIOC Registers Address Map (Continued) (GPIOC_BASE = $00 F310) Register Acronym Address Offset Register Description Reset Value GPIOC_IAR $4 Interrupt Assert Register 0 x 0000 GPIOC_IENR $5 Interrupt Enable Register 0 x 0000 GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOC_IPR $7 Interrupt Pending Register 0 x 0000 GPIOC_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOC_PPMODE $9 Push-Pull Mode Register 0 x 07FF GPIO
Table 4-33 GPIOE Registers Address Map (Continued) (GPIOE_BASE = $00 F330) Register Acronym Address Offset Register Description Reset Value GPIOE_IENR $5 Interrupt Enable Register 0 x 0000 GPIOE_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOE_IPR $7 Interrupt Pending Register 0 x 0000 GPIOE_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOE_PPMODE $9 Push-Pull Mode Register 0 x 3FFF GPIOE_RAWDATA $A Raw Data Input Register — Table 4-34 GPIOF Registers Address Map (GPIOF
Peripheral Memory Mapped Registers Table 4-35 System Integration Module Registers Address Map (SIM_BASE = $00 F350) Register Acronym Address Offset Register Description SIM_CONTROL $0 Control Register SIM_RSTSTS $1 Reset Status Register SIM_SCR0 $2 Software Control Register 0 SIM_SCR1 $3 Software Control Register 1 SIM_SCR2 $4 Software Control Register 2 SIM_SCR3 $5 Software Control Register 3 SIM_MSH_ID $6 Most Significant Half JTAG ID SIM_LSH_ID $7 Least Significant Half JTAG ID
Table 4-37 Flash Module Registers Address Map (Continued) (FM_BASE = $00 F400) Register Acronym Address Offset Register Description Reserved Reserved FMPROT $10 Protection Register (Banked) FMPROTB $11 Protection Boot Register (Banked) Reserved FMUSTAT $13 User Status Register (Banked) FMCMD $14 Command Register (Banked) Reserved Reserved FMOPT 0 $1A 16-Bit Information Option Register 0 Hot temperature ADC reading of Temp Sense; value set during factory test FMOPT 1 $1B 16-Bit Informatio
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym FCRX15MASK_L Address Offset $D Register Description Receive Buffer 15 Mask Low Register Reserved FCSTATUS $10 Error and Status Register FCIMASK1 $11 Interrupt Masks 1 Register FCIFLAG1 $12 Interrupt Flags 1 Register FCR/T_ERROR_CNTRS $13 Receive and Transmit Error Counters Register Reserved Reserved Reserved FCMB0_CONTROL
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym FCMB2_DATA Address Offset $56 Register Description Message Buffer 2 Data Register Reserved FCMB3_CONTROL $58 Message Buffer 3 Control / Status Register FCMB3_ID_HIGH $59 Message Buffer 3 ID High Register FCMB3_ID_LOW $5A Message Buffer 3 ID Low Register FCMB3_DATA $5B Message Buffer 3 Data Register FCMB3_DATA $5C Message Buffer 3 Data Register FCMB3_DATA
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym FCMB6_DATA Address Offset $76 Register Description Message Buffer 6 Data Register Reserved FCMB7_CONTROL $78 Message Buffer 7 Control / Status Register FCMB7_ID_HIGH $79 Message Buffer 7 ID High Register FCMB7_ID_LOW $7A Message Buffer 7 ID Low Register FCMB7_DATA $7B Message Buffer 7 Data Register FCMB7_DATA $7C Messag
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym FCMB10_DATA Address Offset $96 Register Description Message Buffer 10 Data Register Reserved FCMB11_CONTROL $98 Message Buffer 11 Control / Status Register FCMB11_ID_HIGH $99 Message Buffer 11 ID High Register FCMB11_ID_LOW $9A Message Buffer 11 ID Low Register FCMB11_DATA $9B Message Buffer 11 Data Register FCMB11_DATA $9C Message Buffer 11 Data Register
Factory Programmed Memory Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8156 device Register Acronym Address Offset Register Description FCMB14_DATA $B4 Message Buffer 14 Data Register FCMB14_DATA $B5 Message Buffer 14 Data Register FCMB14_DATA $B6 Message Buffer 14 Data Register Reserved FCMB15_CONTROL $B8 Message Buffer 15 Control / Status Register FCMB15_ID_HIGH $B9 Message Buffer 15 ID High Register FCMB15_ID_LOW $BA Mes
• • • • Programmable priority levels for each IRQ Two programmable Fast Interrupts Notification to SIM module to restart clocks out of Wait and Stop modes Drives initial address on the address bus after reset For further information, see Table 4-5, Interrupt Vector Table Contents. 5.3 Functional Description The Interrupt Controller is a slave on the IPBus.
Functional Description 1. See IPIC field definition in Part 5.6.30.2 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt is defined (to the ITCN) by: 1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers 2. Setting the FIMn register to the appropriate vector number 3.
5.4 Block Diagram any0 Priority Level INT1 Level 0 82 -> 7 Priority Encoder 2 -> 4 Decode 7 INT VAB CONTROL IPIC any3 Level 3 Priority Level INT82 82 -> 7 Priority Encoder IACK 7 SR[9:8] PIC_EN 2 -> 4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off.
Register Descriptions system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.2 IPR2 $2 Interrupt Priority Register 2 5.6.3 IPR3 $3 Interrupt Priority Register 3 5.6.4 IPR4 $4 Interrupt Priority Register 4 5.6.
Add.
Register Descriptions 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 15 14 Read 0 0 13 12 BKPT_U0 IPL 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STPCNT IPL Write RESET 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.
5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.
Register Descriptions 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $2 15 14 13 12 11 10 9 8 7 6 Read FMCBE IPL FMCC IPL FMERR IPL LOCK IPL 5 4 0 0 LVI IPL 3 2 1 0 IRQB IPL IRQA IPL 0 0 Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs.
• 11 = IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs.
Register Descriptions • • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $3 Read Write RESET 15 14 13 12 11 10 GPIOD IPL GPIOE IPL GPIOF IPL 0 0 0 0 0 0 9 8 FCMSGBUF IPL 0 0 7 6 FCWKUP IPL 0 0 5 4 FCERR IPL 0 0 3 2 1 0 0 0 0 0 FCBOFF IPL 0 0 Figure 5-6 Interrupt Priority Register 3 (IPR3) 5.6.4.
5.6.4.4 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 Read 15 14 SPI0_RCV IPL Write RESET 0 0 13 12 SPI1_XMIT IPL 0 0 11 10 9 8 7 6 SPI1_RCV IPL 0 0 0 0 0 0 0 0 0 0 5 4 GPIOA IPL 0 0 3 2 1 GPIOB IPL 0 0 0 GPIOC IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs.
• 11 = IRQ is priority level 2 5.6.5.4 Reserved—Bits 9–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.
Register Descriptions They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default.
5.6.6.6 SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.7 SCI 1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.2 Timer D, Channel 3 Interrupt Priority Level (TMRD3 IPL)— Bits 13–12 This field is used to set the interrupt priority level for IRQs.
5.6.7.5 Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.7.
Register Descriptions 5.6.8 Interrupt Priority Register 7 (IPR7) Base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TMRA0 IPL TMRB3 IPL TMRB2 IPL TMRB1 IPL TMRB0 IPL TMRC3 IPL TMRC2 IPL TMRC1 IPL Write RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs.
• • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.5 Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.
Register Descriptions 5.6.9 Interrupt Priority Register 8 (IPR8) Base + $8 Read 15 14 SCI0_RCV IPL Write RESET 0 0 13 12 SCI0_RERR IPL 0 0 11 10 0 0 0 0 9 8 SCI0_TIDL IPL 0 0 7 6 SCI0_XMIT IPL 0 0 5 4 TMRA3 IPL 0 0 3 2 TMRA2 IPL 0 0 1 0 TMRA1 IPL 0 0 Figure 5-11 Interrupt Priority Register 8 (IPR8) 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs.
5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.10 Interrupt Priority Register 9 (IPR9) Base + $9 15 14 13 12 Read PWMA_F IPL PWMB_F IPL Write RESET 0 0 0 0 11 10 PWMA_RL IPL 0 0 9 8 PWM_RL IPL 0 0 7 6 5 4 ADCA_ZC IPL ABCB_ZC IPL 0 0 0 0 3 2 ADCA_CC IPL 0 0 1 0 ADCB_CC IPL 0 0 Figure 5-12 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs.
• 11 = IRQ is priority level 2 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level ADCA_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.
Register Descriptions 5.6.11 Vector Base Address Register (VBA) Base + $A 15 14 13 Read 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 VECTOR BASE ADDRESS Write RESET 0 0 0 0 0 0 0 0 0 0 0 Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.11.
5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $C 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAST INTERRUPT 0 VECTOR ADDRESS LOW Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 0.
Register Descriptions routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table prior to being declared as fast interrupt.
5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.18.2 Reserved—Bit 0 This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing. 5.6.
Register Descriptions 5.6.21 IRQ Pending 3 Register (IRQP3) Base + $14 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [64:49] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.
5.6.23.2 IRQ Pending (PENDING)—Bit 81 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.24 Reserved—Base + 17 5.6.25 Reserved—Base + 18 5.6.26 Reserved—Base + 19 5.6.27 Reserved—Base + 1A 5.6.28 Reserved—Base + 1B 5.6.29 Reserved—Base + 1C 5.6.
Register Descriptions • 11 = Required nested exception priority level is 3 5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.30.
5.7 Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After Reset After reset, all of the ITCN registers are in their default states.
Overview Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features.
6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset operation The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed.
Register Descriptions 6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Address Acronym Register Name Section Location Base + $0 SIM_CONTROL Control Register 6.5.1 Base + $1 SIM_RSTSTS Reset Status Register 6.5.2 Base + $2 SIM_SCR0 Software Control Register 0 6.5.3 Base + $3 SIM_SCR1 Software Control Register 1 6.5.3 Base + $4 SIM_SCR2 Software Control Register 2 6.5.3 Base + $5 SIM_SCR3 Software Control Register 3 6.5.
Add.
Register Descriptions 6.5.1.2 EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset. In addition, this pin can be used as a general purpose input pin after reset.
Base + $1 15 14 13 12 11 10 9 8 7 6 Read 0 0 0 0 0 0 0 0 0 0 5 SWR 4 COPR 3 EXTR 2 1 0 0 0 0 0 POR Write RESET 0 0 0 0 0 0 0 0 0 0 Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) 6.5.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.2.
Register Descriptions Base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Read FIELD Write POR 0 0 0 0 0 0 0 0 Figure 6-5 SIM Software Control Register 0 (SIM_SCR0) 6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR).
6.5.6 SIM Pull-up Disable Register (SIM_PUDR) Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins.
Register Descriptions This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.11 CTRL—Bit 5 This bit controls the pull-up resistors on the WR and RD pins. 6.5.6.12 Reserved—Bit 4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.6.13 JTAG—Bit 3 This bit controls the pull-up resistors on the TRST, TMS and TDI pins. 6.5.6.14 Reserved—Bits 2 - 0 This bit field is reserved or not implemented.
6.5.7.3 • • 0 = Peripheral output function of GPIOB6 is defined to be A22 1 = Peripheral output function of GPIOB6 is defined to be SYS_CLK2 6.5.7.4 • • Alternate GPIOB Peripheral Function for A20 (A20)—Bit 6 0 = Peripheral output function of GPIOB4 is defined to be A20 1 = Peripheral output function of GPIOB4 is defined to be the prescaler_clock (FREF, see Figure 3-4) 6.5.7.
Register Descriptions device); these peripherals work together. The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction with the Quad Timer Status and Control Registers (SCR).
Table 6-2 Control of Pads Using SIM_GPS Control 1 GPIOC_PER GPIOC_DTR SIM_GPS Quad Timer SCR Register OEN bits Control Registers SPI input 1 — 1 — SPI output 1 — 1 — Pin Function Comments See SPI controls for determining the direction of each of the SPI pins. 1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is used for each pin. 2. Reset configuration 3.
Register Descriptions 6.5.8.5 GPIOC0 (C0)—Bit 0 This bit selects the alternate function for GPIOC0. • • 0 = PHASEA1/TB0 (default) 1 = SCLK1 6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power savings feature. The clocks can be individually controlled for each peripheral on the chip.
• 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.7 Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Register Descriptions • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral.
Instruction Portion “Hard Coded” Address Portion 6 Bits from I/O Short Address Mode Instruction 16 Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral registers and then use the I/O Short addressing mode to reference them.
Clock Generation Overview 6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz.
6.8 Stop and Wait Mode Disable Function Permanent Disable D Q D-FLOP C Reprogrammable Disable 56800E STOP_DIS D Q D-FLOP Clock Select C R Reset Note: Wait disable circuit is similar Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this.
Operation with Security Enabled then followed by a 32 clock window in which peripherals are released to implement Flash security, and, finally, followed by a 32 clock window in which the core is initialized. After completion of the described reset sequence, application code will begin execution. Resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock.
• Secure Mode When Flash security is enabled as described in the Flash Memory module specification, the device will boot in internal boot mode, disable all access to external P-space, and start executing code from the Boot Flash at address 0x02_0000. This security affords protection only to applications in which the device operates in internal Flash security mode. Therefore, the security feature cannot be used unless all executing code resides on-chip.
Flash Access Blocking Mechanisms Flash Memory SYS_CLK input 2 clock DIVIDER 7 FMCLKD 7 7 FM_CLKDIV JTAG FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the input clock will be below 12.8MHz, so PRDIV8 = FM_CLKDIV[6] = 0. Using the following equation yields a DIV value of 19 for a clock of 200kHz, and a DIV value of 20 for a clock of 190kHz.
Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 Product Analysis The recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. The customer would need to supply Technical Support with the backdoor key and the protocol to access the backdoor routine in the Flash.
Configuration Table 8-1 56F8356 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8356 A 14 14 14 pins - EMI Address pins EMI Address B 8 1 1 pin - EMI Address pin 7 pins - EMI Address pins - Not available in this package EMI Address N/A C 11 11 4 pins -DEC1 / TMRB / SPI1 4 pins -DEC0 / TMRA 3 pins -PWMA current sense DEC1 / TMRB DEC0 / TMRA PWMA current sense D 13 9 2 pins - EMI CSn 4 pins - EMI CSn - Not available in this package 2 pins - SCI1 2 pins - EMI CSn 3 pins
Table 8-2 56F8156 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8156 E 14 11 2 pins - SCI0 2 pins - EMI Address pins 4 pins - SPI0 1 pin - TMRC 1 pin - TMRC - Not available in this package 2 pins - Dedicated GPIO 2 pins - TMRD - Not available in this package SCI0 EMI Address SPI0 TMRC N/A GPIO N/A F 16 16 16 pins - EMI Data EMI Data Peripheral Function Reset Function 56F8356 Technical Data, Rev.
Configuration Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIO Bit Reset Function Functional Signal Package PIn 0 Peripheral A8 19 1 Peripheral A9 20 2 Peripheral A10 21 3 Peripheral A11 22 4 Peripheral A12 23 5 Peripheral A13 24 6 Peripheral A14 25 7 Peripheral A15 26 8 Peripheral A0 138 9 Peripheral A1 10 10 Peripheral A2 11 11 Peripheral A3
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIO Bit Reset Function Functional Signal Package PIn 1 This is a function of the EMI_MODE, EXTBOOT and Flash security settings at reset.
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIOD GPIO Bit Reset Function Functional Signal Package PIn 0 GPIO CS2 48 1 GPIO CS3 49 2 N/A 3 N/A 4 N/A 5 N/A 6 Peripheral TXD1 42 7 Peripheral RXD1 43 8 Peripheral PS / CS0 46 9 Peripheral DS / CS1 47 10 Peripheral ISB0 50 11 Peripheral ISB1 52 12 Peripheral ISB2 53 0 Per
Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIO Bit Reset Function Functional Signal Package PIn 0 Peripheral D7 28 1 Peripheral D8 29 2 Peripheral D9 30 3 Peripheral D10 32 4 Peripheral D11 133 5 Peripheral D12 134 6 Peripheral D13 135 7 Peripheral D14 136 8 Peripheral D15 137 9 Peripheral D0 59 10 Peripheral D1 60 11 Peripheral D
General Characteristics of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels combined with the ability to receive 5V levels without damage.
Table 10-1 Absolute Maximum Ratings (Continued) (VSS = VSSA_ADC = 0) Characteristic Symbol Notes Min Max Unit VOD Pin Group 4 -0.3 6.0 V Output Voltage (open drain) Ambient Temperature (Automotive) TA -40 125 °C Ambient Temperature (Industrial) TA -40 105 °C Junction Temperature (Automotive) TJ -40 150 °C Junction Temperature (Industrial) TJ -40 125 °C Storage Temperature (Automotive) TSTG -55 150 °C Storage Temperature (Industrial) TSTG -55 150 °C 1.
General Characteristics Table 10-3 Thermal Characteristics6 Value Comments Characteristic Symbol Unit Notes 144-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 47.1 °C/W 2 RθJMA 43.8 °C/W 2 Junction to ambient Natural convection Four layer board (2s2p) RθJMA (2s2p) 40.8 °C/W 1,2 Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 39.2 °C/W 1,2 Junction to case RθJC 11.
Table 10-4 Recommended Operating Conditions (VREFLO = 0V, VSS = VSSA_ADC = 0V, VDDA = VDDA_ADC = VDDA_OSC_PLL ) Characteristic ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes Min Typ Max Unit VDDA_ADC, VREFH VREFH must be less than 3 3.3 3.6 V 3 3.3 3.6 V 2.25 2.5 2.
DC Electrical Characteristics Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH = IOHmax Output Low Voltage VOL — — 0.4 V IOL = IOLmax IIH Pin Groups 1, 2, 5, 6, 9 — 0 +/- 2.5 μA VIN = 3.0V to 5.5V IIH Pin Group10 40 80 160 μA VIN = 3.0V to 5.5V IIHA Pin Group 13 — 0 +/- 2.
Table 10-6 Power on Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. When VDD_CORE drops below VEI2.5, an interrupt is generated. 2. When VDD_CORE drops below VEI3.3, an interrupt is generated.
DC Electrical Characteristics Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) Mode RUN1_MAC IDD_Core IDD_IO1 IDD_ADC IDD_OSC_PLL 150mA 13μA 50mA 2.5mA Test Conditions • 60MHz Device Clock • All peripheral clocks are enabled • All peripherals running • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 86mA 13μA 70μA 2.
Table 10-10. PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start-up time TPS 0.3 0.5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms Min-Max Period Variation TPV 120 — 200 ps Peak-to-Peak Jitter TPJ — — 175 ps Bias Current IBIAS — 1.5 2 mA IPD — 100 150 μA Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8156 device.
AC Electrical Characteristics 10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-1. Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH – VIL)/2.
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes. 10.5 External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 fosc 0 — 120 MHz Clock Pulse Width3 tPW 3.
Crystal Oscillator Timing 3. This is the minimum time required after the PLL set up is changed to ensure reliable operation. 10.7 Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit Crystal Start-up time TCS 4 5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms RESR — — 120 ohms Crystal Peak-to-Peak Jitter TD 70 — 250 ps Crystal Min-Max Period Variation TPV 0.12 — 1.
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler clock and prescaler set to ÷ 1), the EMI quadrature clock is generated using both edges of the EXTAL clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE and DCAEO are used to make this duty cycle adjustment where needed. DCAOE and DCAEO are calculated as follows: DCAOE = 0.
External Memory Interface Timing Note: When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Symbol tAWR tWR Data Out Valid to WR Asserted tDWR Wait States Configuration D M Wait States Controls Unit WWS=0 -1.477 0.50 WWS>0 -1.564 0.75 + DCAOE WWSS ns WWS=0 -0.186 0.25 + DCAOE WWS>0 -0.
Table 10-16 External Memory Interface Timing (Continued) Characteristic Symbol RD Deasserted to RD Asserted tRDRD WR Deasserted to WR Asserted tWRWR RD Deasserted to WR Asserted Wait States Configuration tRDWR D M Wait States Controls Unit -0.2342 0.00 RWSS,RWSH MDAR3, 4 ns WWS=0 -1.279 0.75 + DCAEO WWS>0 -0.938 1.00 WWSS, WWSH ns WWS=0 -0.046 0.50 WWS>0 0.052 0.75 + DCAOE RWSH, WWSS, MDAR3 ns 1. N/A since device captures data before it deasserts RD 2.
Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 (Continued) Characteristic Symbol Typical Min Typical Max Unit See Figure tIW 1.5T — ns 10-9 IRQA Width Assertion to Recover from Stop State5 1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. 3.
A0–A15 First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 10-7 External Level-Sensitive Interrupt Timing IRQA , IRQB tIRI A0–A15 First Interrupt Vector Instruction Fetch Figure 10-8 Interrupt from Wait State Timing tIW IRQA tIF A0–A15 First Instruction Fetch Not IRQA Interrupt Vector Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 56F8356 Technical Data, Rev
Serial Peripheral Interface (SPI) Timing 10.10 Serial Peripheral Interface (SPI) Timing Table 10-18 SPI Timing1 Characteristic Symbol Cycle time Master Slave Min Max Unit 50 50 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 25 — — ns ns 24.1 25 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.
Table 10-18 SPI Timing1 (Continued) Characteristic Symbol Fall time Master Slave Min Max Unit — — 9.7 9.0 ns ns See Figure 10-10, 10-11, 10-12, 10-13 tF 1. Parameters listed are guaranteed by design.
Serial Peripheral Interface (SPI) Timing SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in Bits 14–1 tDI tDV(ref) MOSI (Output) tDH Master MSB out tDV Bits 14– 1 tF LSB in tDI(ref) Master LSB out tR Figure 10-11 SPI Master Timing (CPHA = 1) 56F8356 Technical Data, Rev.
SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tDV tDH MSB in tF tR Bits 14–1 tDS MOSI (Input) tELG Bits 14–1 tD Slave LSB out tDI tDI LSB in Figure 10-12 SPI Slave Timing (CPHA = 0) 56F8356 Technical Data, Rev.
Quad Timer Timing SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) tD tF Slave MSB out Bits 14–1 tDS tDV tDI tDH MOSI (Input) MSB in Slave LSB out Bits 14–1 LSB in Figure 10-13 SPI Slave Timing (CPHA = 1) 10.
Timer Inputs PIN PINHL PINHL POUTHL POUTHL Timer Outputs POUT Figure 10-14 Timer Timing 10.12 Quadrature Decoder Timing Table 10-20 Quadrature Decoder Timing1, 2 Characteristic Symbol Min Max Unit See Figure Quadrature input period PIN 4T + 12 — ns 10-15 Quadrature input high / low period PHL 2T + 6 — ns 10-15 Quadrature phase period PPH 1T + 3 — ns 10-15 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns. 2.
Serial Communication Interface (SCI) Timing 10.13 Serial Communication Interface (SCI) Timing Table 10-21 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-16 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-17 Baud Rate2 1. Parameters listed are guaranteed by design. 2. fMAX is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8356 device and 40MHz for the 56F8156 device.
CAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-18 Bus Wake Up Detection 10.
Analog-to-Digital Converter (ADC) Parameters TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 10-20 Test Access Port Timing Diagram TRST (Input) tTRST Figure 10-21 TRST Timing Diagram 10.
Table 10-24 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit ADC reference circuit power-up time4 tVREF — — 25 ms Conversion time tADC — 6 — tAIC cycles3 Sample time tADS — 1 — tAIC cycles3 Input capacitance CADI — 5 — pF Input injection current5, per pin IADI — — 3 mA Input injection current, total IADIT — — 20 mA VREFH current IVREFH — 1.
Analog-to-Digital Converter (ADC) Parameters Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error.
10.17 Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to VREFH - VREFH / 2, while the other charges to the analog input voltage.
Power Consumption 3. 4. Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time; 1pf Figure 10-23 Equivalent Circuit for A/D Loading 10.18 Power Consumption This section provides additional detail which can be used to optimize power consumption for a given application.
where: • • • Summation is performed over all output pins with capacitive loads TotalPower is expressed in mW Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. The one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate. In this case, power from these buses can be significant.
56F8356 Package and Pin-Out Information Part 11 Packaging 11.1 56F8356 Package and Pin-Out Information VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 CAN_RX CAN_TX VPPI TDO TDI TMS TCK TRST VDD_IO TC0 TD1 TD0 ISA2 ISA1 ISA0 EXTBOOT ANB7 ANB6 ANB5 This section contains package and pin-out information for the 56F8356. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP).
Table 11-1 56F8356 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8156 Package and Pin-Out Information Table 11-1 56F8356 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
VSS EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 NC NC VPPI TDO TDI TMS TCK TRST VDD_IO TC0 GPIOE11 GPIOE10 GPIOC10 GPIOC9 GPIOC8 EXTBOOT ANB7 ANB6 ANB5 Orientation Mark VDD_IO VPP2 CLKO TXD0 RXD0 SCLK1 MOSI1 MISO1 SS1 A1 A2 A3 A4 A5 VCAP4 VDD_IO A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS D7 D8 D9 VDD_IO D10 GPIOB0 PWMB0 PWMB1 PWMB2 ANB4 ANB3 ANB2 ANB1 ANB0 VSSA_ADC VDDA_ADC VREFH VREFP VREFMID VREFN VREFLO NC ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET
56F8156 Package and Pin-Out Information Table 11-2 56F8156 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 11-2 56F8156 144-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8156 Package and Pin-Out Information 0.20 H B-C D 4X 144 PIN 1 INDEX 0.20 A B-C D 4X 36 TIPS 109 1 108 4X A A E1 C B 4 CL 5 E 7 140X E1/2 36 3 X X=B, C or D e VIEW A E/2 VIEW A e/2 73 37 72 D NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS B, C AND D TO BE DETERMINED AT DATUM H. 4. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE SIZE BY A MAXIMUM OF 0.1 mm. 5.
Please see www.freescale.com for the most current case outline. Part 12 Design Considerations 12.
Electrical Design Considerations where: TT = Thermocouple temperature on top of package (oC) ΨJT = Thermal characterization parameter (oC)/W PD = Power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package.
• • • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.
Power Distribution and I/O Ring Implementation VDDA_OSC_PLL VDDA_ADC VDD REG VCAP REG I/O ADC CORE OSC VSS VREFH VREFP VREFMID VREFN VREFLO VSSA_ADC Figure 12-1 Power Management Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts.
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