56F8357/56F8157 Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8357 Rev. 15 01/2007 freescale.
Document Revision History Version History Description of Change Rev 1.0 Initial Public Release Rev 2.0 Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added “Typical Min” values to Table 10-17. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters Table 10-9; External Clock Operation Timing Requirements Table 10-13; SPI Timing Table 10-18; ADC Parameters Table 10-24; and IO Loading Coefficients at 10MHz Table 10-25.
Document Revision History (Continued) Version History Rev. 15 Description of Change • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Added the following note to the description of the TRST signal in Table 2-2: Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. Please see http://www.freescale.
56F8357/56F8157 General Description Note: Features in italics are NOT available in the 56F8157 device.
Table of Contents Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 6 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8357/56F8157 Features . . . . . . . . . . . . . 6 Device Description . . . . . . . . . . . . . . . . . . . . 8 Award-Winning Development Environmen . 10 Architecture Block Diagram . . . . . . . . . . . . . 11 Product Documentation . . . . . . . . . . . . . . . 15 Data Sheet Conventions . . . . . . . . . . . . . . 15 Part 2: Signal/Connection Descriptions . . . 16 2.1. Introduction . . . . . .
Part 1 Overview 1.1 56F8357/56F8157 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
56F8357/56F8157 Features 1.1.3 Memory Note: Features in italics are NOT available in the 56F8157 device.
• • Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) Two Serial Peripheral Interfaces (SPIs). both with configurable 4-pin port (or eight additional GPIO lines); SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B — In the 56F8357, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B — In the 56F8157, SPI1 can alternately be used only as GPIO • • • • • • • • 1.1.
Device Description 1.2.1 56F8357 Features The 56F8357 controller includes 256KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. It also supports program execution from external memory. A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas.
A key application-specific feature of the 56F8157 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control.
Architecture Block Diagram 1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8157 device and are shaded in the following figures. The 56F8357/56F8157 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E system buses communicate with internal memories, the external memory interface and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E architecture and provides a brief description of their function.
5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw_m[31:0] Program RAM 56800E 24 CHIP TAP Controller EMI 16 10 TAP Linking Module xab1[23:0] Address Data Control Data RAM xab2[23:0] External JTAG Port Data Flash cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge To Flash Control Logic Flash Memory Module NOT available on the 56F8157 device. IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Memory (FM) Module.
Architecture Block Diagram To/From IPBus Bridge Interrupt Controller CLKGEN (OSC/PLL) Low Voltage Interrupt Timer A 4 POR & LVI System POR Quadrature Decoder 0 4 RESET SIM Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 SPI 1 13 PWMA SYNC Output GPIO A 13 PWMB GPIO B SYNC Output GPIO C ch3i ch2i 2 Timer C GPIO D ch3o ch2o GPIO E GPIO F 4 SPI 0 2 SCI 0 2 ADCB 8 8 ADCA TEMP_SENSE SCI 1 NOT available on the 56F8157 device.
Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
Product Documentation 1.5 Product Documentation The documents in Table 1-2 are required for a complete description and proper design. with the 56F8357/56F8157 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8357 and 56F8157 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin.
Introduction VDD_IO Power VDDA_OSC_PLL VDDA_ADC Power Power VSS VSSA_ADC Ground Ground OCR_DIS VCAP1 - VCAP4 Other Supply Ports VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO PLL and Clock A0 - A5 (GPIOA8 - 13) A6 - A7 (GPIOE2 - 3) External Address Bus or GPIO A8 - A15 (GPIOA0 - 7) GPIOB0 - 3 (A16 - 19) GPIOB4 (A20, prescaler_clock) GPIOB5 (A21, SYS_CLK) GPIOB6 (A22, SYS_CLK2) GPIOB7 (A23, oscillator_clock) External Data Bus D0 - D6 (GPIOF9 - 15) D7 - D15 (GPIOF0 - 8) RD External Bus Control WR PS / CS
Power Power Power Ground Ground VDD_IO 7 1 1 6 VDDA_OSC_PLL VDDA_ADC VSS VSSA_ADC 1 OCR_DIS Other Supply Ports PLL and Clock 1 VCAP1 - VCAP4 4 VPP1 & VPP2 2 CLKMODE EXTAL XTAL CLKO A0 - A5 (GPIOA8 - 13) A6 - A7 (GPIOE2 - 3) External Address Bus or GPIO A8 - A15 (GPIOA0 - 7) GPIOB0 - 3 (A16 - 19) GPIOB4 (A20, prescaler_clock) 1 1 1 1 1 1 1 1 1 1 1 1 2 8 3 6 3 4 D7 - D15 (GPIOF0 - 8) (SCLK1, GPIOC0) (MOSI1, GPIOC1) (MISO1, GPIOC2) (SS1, GPIOC3) SPI 1 or GPIO (GPIOC8 - 10) GPIO PWM
Signal Pins 2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Note: Signals in italics are NOT available in the 56F8157 device. Note: The 160 Map Ball Grid Array is not available in the 56F8157 device. If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA State During Reset Signal Name Pin No. Ball No. Type VSS 27 J4 Supply VSS 41 K11 VSS — These pins provide ground for chip logic and I/O drivers. VSS 74 G11 VSS 80 E7 VSS 125 J11 VSS 160 E6 VSSA_ADC 115 D12 Supply ADC Analog Ground — This pin supplies an analog ground to the ADC modules.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type XTAL 93 K12 Input/ Output State During Reset Chip-driven Signal Description Crystal Oscillator Output — This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to GND. The input clock can be selected to provide the clock directly to the core.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type A6 17 G1 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Address Bus — A6 - A7 specify two of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A6–A7 and EMI control signals are tri-stated when the external bus is inactive.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type State During Reset GPIOB0 33 L1 Schmitt Input/ Output Input, pull-up enabled (A16) Output GPIOB1 (A17) 34 GPIOB2 (A18) 35 L2 GPIOB3 (A19) 36 M1 Signal Description Port B GPIO — These four GPIO pins can be programmed as input or output pins. Address Bus — A16 - A19 specify one of the address lines for external program or data memory accesses.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type D0 70 P10 Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Bus — D0 - D6 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), D0 - D6 and EMI control signals are tri-stated when the external bus is inactive.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type D7 28 K1 Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Data Bus — D7 - D14 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), D7 - D15and EMI control signals are tri-stated when the external bus is inactive.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type WR 51 L4 Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Write Enable — WR is asserted during external memory write cycles. When WR is asserted low, pins D0 - D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type GPIOD0 55 P6 Input/ Output State During Reset Input, pull-up enabled Output (CS2) GPIOD1 (CS3) 56 L6 GPIOD2 (CS4) 57 K6 GPIOD3 (CS5) 58 N7 GPIOD4 (CS6) 59 P7 GPIOD5 (CS7) 60 L7 Signal Description Port D GPIO — These six GPIO pins can be individually programmed as input or output pins.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type TXD1 49 P4 Output (GPIOD6) Input/ Output State During Reset In reset, output is disabled, pull-up is enabled Signal Description Transmit Data — SCI1 transmit data output Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOD_PUR register.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type TRST 136 D9 Schmitt Input State During Reset Input, pulled high internally Signal Description Test Reset — As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type INDEX0 157 A1 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index — Quadrature Decoder 0, INDEX input (TA2) Schmitt Input/ Output TA2 — Timer A, Channel 2 (GPIOC6) Schmitt Input/ Output Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX0.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type MOSI0 148 B6 Input/ Output (GPIOE5) State During Reset In reset, output is disabled, pull-up is enabled Input/ Output Signal Description SPI 0 Master Out/Slave In — This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type PHASEA1 6 C1 Schmitt Input State During Reset Input, pull-up enabled Signal Description Phase A1 — Quadrature Decoder 1, PHASEA input for decoder 1. (TB0) Schmitt Input/ Output TB0 — Timer B, Channel 0 (SCLK1) Schmitt Input/ Output SPI 1 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type INDEX1 8 E2 Schmitt Input State During Reset Input, pull-up enabled Signal Description Index1 — Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output TB2 — Timer B, Channel 2 (MISO1) Schmitt Input/ Output SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA State During Reset Signal Name Pin No. Ball No. Type PWMA0 73 M11 Output PWMA0 - 5 — These are six PWMA outputs.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA State During Reset Signal Name Pin No. Ball No.
Signal Pins Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type State During Reset TD0 129 B10 Schmitt Input/ Output Input, pull-up enabled (GPIOE10) TD1 (GPIOE11) 130 A10 TD2 (GPIOE12) 131 D10 TD3 (GPIOE13) 132 E10 IRQA 65 K9 IRQB 66 P9 Signal Description TD0 - 3 — Timer D, Channels 0, 1, 2 and 3 Port E GPIO — These GPIO pins can be individually programmed as input or output pins.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA Signal Name Pin No. Ball No. Type EXTBOOT 124 B11 Schmitt Input State During Reset Input, pull-up enabled Signal Description External Boot — This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4.
Introduction Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference from the OCCS chapter of the 56F8300 Peripheral User Manual.
crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
Registers 3.2.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-4. The external clock source is connected to XTAL and the EXTAL pin is grounded. When using an external clock source, set the OCCS_COHL bit high as well. XTAL EXTAL External Clock VSS Note: When using an external clocking source with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL register should be set to 1.
4.2 Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have an effect on the P-space memory map, as shown in Table 4-3.
Interrupt Vector Table Table 4-4 Program Memory Map at Reset Begin/End Address P:$1F FFFF P:$10 0000 Mode 0 (MA = 0) Mode 11 (MA = 1) Internal Boot External Boot Internal Boot 16-Bit External Address Bus External Program Memory5 EMI_MODE = 02,3 16-Bit External Address Bus External Program Memory5 EMI_MODE = 14 20-Bit External Address Bus External Program Memory5 P:$0F FFFF P:$03 0000 P:$02 FFFF P:$02 F800 On-Chip Program RAM 4KB P:$02 F7FF P:$02 2000 Reserved 116KB P:$02 1FFF P:$02 0000 Boot
Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the 56F8157 device.
Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + GPIOB 34 0-2 P:$44 GPIOB GPIOA 35 0-2 P:$46 GPIOA Peripheral Interrupt Function Reserved SPI1 38 0-2 P:$4C SPI 1 Receiver Full SPI1 39 0-2 P:$4E SPI 1 Transmitter Empty SPI0 40 0-2 P:$50 SPI 0 Receiver Full SPI0 41 0-2 P:$52 SPI 0 Transmitter Empty SCI1 42 0-2 P:$54 SCI 1 Transmitter Empty SCI1 43 0-2 P:$56 SCI 1 Transmitter Idle Reserv
Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + ADCA 74 0-2 P:$94 ADC A Conversion Complete / End of Scan ADCB 75 0-2 P:$96 ADC B Zero Crossing or Limit Error ADCA 76 0-2 P:$98 ADC A Zero Crossing or Limit Error Peripheral Interrupt Function PWMB 77 0-2 P:$9A Reload PWM B PWMA 78 0-2 P:$9C Reload PWM A PWMB 79 0-2 P:$9E PWM B Fault PWMA 80 0-2 P:$A0 PWM A Fault core 81 -1 P:$A2 SW Interrupt LP 1.
Flash Memory Map 4.5 Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately by its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations.
Table 4-7 Flash Memory Partitions Flash Size Sectors Sector Size Page Size Program Flash 256KB 16 8K x 16 bits 512 x 16 bits Data Flash 8KB 16 256 x 16 bits 256 x 16 bits Boot Flash 16KB 4 2K x 16 bits 256 x 16 bits Please see 56F8300 Peripheral User Manual for additional Flash information. 4.
Peripheral Memory Mapped Registers Table 4-8 EOnCE Memory Map (Continued) Address Register Acronym Register Name X:$FF FFFD OTXRXSR (8 bits) Transmit and Receive Status and Control Register X:$FF FFFE OTX / ORX (32 bits) Transmit Register / Receive Register X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word Receive Register Upper Word 4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series.
Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number SPI #0 SPI0 X:$00 F2A0 4-25 SPI #1 SPI1 X:$00 F2B0 4-26 COP COP X:$00 F2C0 4-27 PLL, OSC CLKGEN X:$00 F2D0 4-28 GPIO Port A GPIOA X:$00 F2E0 4-29 GPIO Port B GPIOB X:$00 F300 4-30 GPIO Port C GPIOC X:$00 F310 4-31 GPIO Port D GPIOD X:$00 F320 4-32 GPIO Port E GPIOE X:$00 F330 4-33 GPIO Port F GPIOF X:$00 F340 4-34 SIM SIM X:$00 F350 4-35 Power Supe
Peripheral Memory Mapped Registers Table 4-10 External Memory Integration Registers Address Map (Continued) (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description Reset Value CSOR 0 $8 Chip Select Option Register 0 0x5FCB programmed for chip select for program space, word wide, read and write, 11 waits CSOR 1 $9 Chip Select Option Register 1 0x5FAB programmed for chip select for data space, word wide, read and write, 11 waits CSOR 2 $A Chip Select Option Register 2 CSOR 3
Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and Control Register Reserved TMRA1_CMP1 $10 Compare Register 1 TMRA1_CMP2 $11 Compare Register 2 TMRA1_CAP $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNTR $15 Counter Register TMRA1_CTR
Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA3_CTRL $36 Control Register TMRA3_SCR $37 Status and Control Register TMRA3_CMPLD1 $38 Comparator Load Register 1 TMRA3_CMPLD2 $39 Comparator Load Register 2 TMRA3_COMSCR $3A Comparator Status and Control Register Table 4-12 Quad Timer B Registers Address Map (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the
Table 4-12 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F080) Quad Timer B is NOT available in the 56F8157 device Register Acronym Address Offset Register Description TMRB2_CMP1 $20 Compare Register 1 TMRB2_CMP2 $21 Compare Register 2 TMRB2_CAP $22 Capture Register TMRB2_LOAD $23 Load Register TMRB2_HOLD $24 Hold Register TMRB2_CNTR $25 Counter Register TMRB2_CTRL $26 Control Register TMRB2_SCR $27 Status and Control Register TMRB2_CMPLD1 $28 Comparator Load R
Peripheral Memory Mapped Registers Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC0_CTRL $6 Control Register TMRC0_SCR $7 Status and Control Register TMRC0_CMPLD1 $8 Comparator Load Register 1 TMRC0_CMPLD2 $9 Comparator Load Register 2 TMRC0_COMSCR $A Comparator Status and Control Register Reserved TMRC1_CMP1 $10 Compare Register 1 TMRC1_CMP2 $11 Compare Register 2 TMRC1_CAP $12 Capture Regi
Table 4-13 Quad Timer C Registers Address Map (Continued) (TMRC_BASE = $00 F0C0) Register Acronym Address Offset Register Description TMRC3_HOLD $34 Hold Register TMRC3_CNTR $35 Counter Register TMRC3_CTRL $36 Control Register TMRC3_SCR $37 Status and Control Register TMRC3_CMPLD1 $38 Comparator Load Register 1 TMRC3_CMPLD2 $39 Comparator Load Register 2 TMRC3_COMSCR $3A Comparator Status and Control Register Table 4-14 Quad Timer D Registers Address Map (TMRD_BASE = $00 F100) Quad T
Peripheral Memory Mapped Registers Table 4-14 Quad Timer D Registers Address Map (Continued) (TMRD_BASE = $00 F100) Quad Timer D is NOT available in the 56F8157 device Register Acronym TMRD1_COMSCR Address Offset $1A Register Description Comparator Status and Control Register Reserved TMRD2_CMP1 $20 Compare Register 1 TMRD2_CMP2 $21 Compare Register 2 TMRD2_CAP $22 Capture Register TMRD2_LOAD $23 Load Register TMRD2_HOLD $24 Hold Register TMRD2_CNTR $25 Counter Register TMRD2_CTRL $26
Table 4-15 Pulse Width Modulator A Registers Address Map (PWMA_BASE = $00 F140) PWMA is NOT available in the 56F8157 device Register Acronym Address Offset Register Description PWMA_PMCTL $0 Control Register PWMA_PMFCTL $1 Fault Control Register PWMA_PMFSA $2 Fault Status Acknowledge Register PWMA_PMOUT $3 Output Control Register PWMA_PMCNT $4 Counter Register PWMA_PWMCM $5 Counter Modulo Register PWMA_PWMVAL0 $6 Value Register 0 PWMA_PWMVAL1 $7 Value Register 1 PWMA_PWMVAL2 $8
Peripheral Memory Mapped Registers Table 4-16 Pulse Width Modulator B Registers Address Map (Continued) (PWMB_BASE = $00 F160) Register Acronym Address Offset Register Description PWMB_PWMVAL1 $7 Value Register 1 PWMB_PWMVAL2 $8 Value Register 2 PWMB_PWMVAL3 $9 Value Register 3 PWMB_PWMVAL4 $A Value Register 4 PWMB_PWMVAL5 $B Value Register 5 PWMB_PMDEADTM $C Dead Time Register PWMB_PMDISMAP1 $D Disable Mapping Register 1 PWMB_PMDISMAP2 $E Disable Mapping Register 2 PWMB_PMCFG $
Table 4-18 Quadrature Decoder 1 Registers Address Map (DEC1_BASE = $00 F190) Quadrature Decoder 1 is NOT available in the 56F8157 device Register Acronym Address Offset Register Description DEC1_DECCR $0 Decoder Control Register DEC1_FIR $1 Filter Interval Register DEC1_WTR $2 Watchdog Time-out Register DEC1_POSD $3 Position Difference Counter Register DEC1_POSDH $4 Position Difference Counter Hold Register DEC1_REV $5 Revolution Counter Register DEC1_REVH $6 Revolution Hold Register
Peripheral Memory Mapped Registers Table 4-19 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F1A0) Register Acronym Address Offset Register Description FIM1 $E Fast Interrupt Match Register 1 FIVAL1 $F Fast Interrupt Vector Address Low 1 Register FIVAH1 $10 Fast Interrupt Vector Address High 1 Register IRQP 0 $11 IRQ Pending Register 0 IRQP 1 $12 IRQ Pending Register 1 IRQP 2 $13 IRQ Pending Register 2 IRQP 3 $14 IRQ Pending Register 3 IRQP 4 $15 IRQ Pending
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) (ADCA_BASE = $00 F200) Register Acronym Address Offset Register Description ADCA_LLMT 2 $13 Low Limit Register 2 ADCA_LLMT 3 $14 Low Limit Register 3 ADCA_LLMT 4 $15 Low Limit Register 4 ADCA_LLMT 5 $16 Low Limit Register 5 ADCA_LLMT 6 $17 Low Limit Register 6 ADCA_LLMT 7 $18 Low Limit Register 7 ADCA_HLMT 0 $19 High Limit Register 0 ADCA_HLMT 1 $1A High Limit Register 1 ADCA_HLMT 2 $1B High Limit Register
Peripheral Memory Mapped Registers Table 4-21 Analog-to-Digital Converter Registers Address Map (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_CR 1 $0 Control Register 1 ADCB_CR 2 $1 Control Register 2 ADCB_ZCC $2 Zero Crossing Control Register ADCB_LST 1 $3 Channel List Register 1 ADCB_LST 2 $4 Channel List Register 2 ADCB_SDIS $5 Sample Disable Register ADCB_STAT $6 Status Register ADCB_LSTAT $7 Limit Status Register ADCB_ZCSTAT $8 Zero Cross
Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) (ADCB_BASE = $00 F240) Register Acronym Address Offset Register Description ADCB_HLMT 5 $1E High Limit Register 5 ADCB_HLMT 6 $1F High Limit Register 6 ADCB_HLMT 7 $20 High Limit Register 7 ADCB_OFS 0 $21 Offset Register 0 ADCB_OFS 1 $22 Offset Register 1 ADCB_OFS 2 $23 Offset Register 2 ADCB_OFS 3 $24 Offset Register 3 ADCB_OFS 4 $25 Offset Register 4 ADCB_OFS 5 $26 Offset Register 5 ADCB_OFS 6 $27 Offs
Peripheral Memory Mapped Registers Table 4-24 Serial Communication Interface 1 Registers Address Map (SCI1_BASE = $00 F290) Register Acronym Address Offset Register Description SCI1_SCIBR $0 Baud Rate Register SCI1_SCICR $1 Control Register Reserved SCI1_SCISR $3 Status Register SCI1_SCIDR $4 Data Register Table 4-25 Serial Peripheral Interface 0 Registers Address Map (SPI0_BASE = $00 F2A0) Register Acronym Address Offset Register Description SPI0_SPSCR $0 Status and Control Register S
Table 4-28 Clock Generation Module Registers Address Map (CLKGEN_BASE = $00 F2D0) Register Acronym Address Offset Register Description PLLCR $0 Control Register PLLDB $1 Divide-By Register PLLSR $2 Status Register Reserved SHUTDOWN $4 Shutdown Register OSCTL $5 Oscillator Control Register Table 4-29 GPIOA Registers Address Map (GPIOA_BASE = $00 F2E0) Register Acronym Address Offset Register Description Reset Value GPIOA_PUR $0 Pull-up Enable Register 0 x 3FFF GPIOA_DR $1 Data Reg
Peripheral Memory Mapped Registers Table 4-30 GPIOB Registers Address Map (Continued) (GPIOB_BASE = $00 F300) Register Acronym Address Offset Register Description Reset Value GPIOB_IAR $4 Interrupt Assert Register 0 x 0000 GPIOB_IENR $5 Interrupt Enable Register 0 x 0000 GPIOB_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOB_IPR $7 Interrupt Pending Register 0 x 0000 GPIOB_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000 GPIOB_PPMODE $9 Push-Pull Mode Register 0 x 00FF GPIO
Table 4-32 GPIOD Registers Address Map (GPIOD_BASE = $00 F320) Register Acronym Address Offset Register Description Reset Value GPIOD_PUR $0 Pull-up Enable Register 0 x 1FFF GPIOD_DR $1 Data Register 0 x 0000 GPIOD_DDR $2 Data Direction Register 0 x 0000 GPIOD_PER $3 Peripheral Enable Register 0 x 1FC0 GPIOD_IAR $4 Interrupt Assert Register 0 x 0000 GPIOD_IENR $5 Interrupt Enable Register 0 x 0000 GPIOD_IPOLR $6 Interrupt Polarity Register 0 x 0000 GPIOD_IPR $7 Interrupt Pe
Peripheral Memory Mapped Registers Table 4-34 GPIOF Registers Address Map (GPIOF_BASE = $00 F340) Register Acronym Address Offset Register Description Reset Value GPIOF_PUR $0 Pull-up Enable Register 0 x FFFF GPIOF_DR $1 Data Register 0 x 0000 GPIOF_DDR $2 Data Direction Register 0 x 0000 GPIOF_PER $3 Peripheral Enable Register 0 x FFFF GPIOF_IAR $4 Interrupt Assert Register 0 x 0000 GPIOF_IENR $5 Interrupt Enable Register 0 x 0000 GPIOF_IPOLR $6 Interrupt Polarity Register 0
Table 4-36 Power Supervisor Registers Address Map (LVI_BASE = $00 F360) Register Acronym Address Offset Register Description LVI_CONTROL $0 Control Register LVI_STATUS $1 Status Register Table 4-37 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FMCLKD $0 Clock Divider Register FMMCR $1 Module Control Register Reserved FMSECH $3 Security High Half Register FMSECL $4 Security Low Half Register Reserved Reserved FMPROT $10
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8157 device Register Acronym FCMCR Address Offset $0 Register Description Module Configuration Register Reserved FCCTL0 $3 Control Register 0 Register FCCTL1 $4 Control Register 1 Register FCTMR $5 Free-Running Timer Register FCMAXMB $6 Maximum Message Buffer Configuration Register Reserved FCRXGMASK_H $8 Receive Global Mask High Register FCRXGMASK_L $9 Rec
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description FCMSB1_ID_LOW $4A Message Buffer 1 ID Low Register FCMB1_DATA $4B Message Buffer 1 Data Register FCMB1_DATA $4C Message Buffer 1 Data Register FCMB1_DATA $4D Message Buffer 1 Data Register FCMB1_DATA $4E Message Buffer 1 Data Register Reserved FCMB2_CONTROL $50 Message Buffer 2 Control / Status Register FCMB2_ID_HIG
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description FCMB5_ID_HIGH $69 Message Buffer 5 ID High Register FCMB5_ID_LOW $6A Message Buffer 5 ID Low Register FCMB5_DATA $6B Message Buffer 5 Data Register FCMB5_DATA $6C Message Buffer 5 Data Register FCMB5_DATA $6D Message Buffer 5 Data Register FCMB5_DATA $6E Message Buffer 5 Data Regis
Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description FCMB9_CONTROL $88 Message Buffer 9 Control / Status Register FCMB9_ID_HIGH $89 Message Buffer 9 ID High Register FCMB9_ID_LOW $8A Message Buffer 9 ID Low Register FCMB9_DATA $8B Message Buffer 9 Data Register FCMB9_DATA $8C Message Buffer 9 Data Register FCMB9_DATA $8D Message Buffer 9 Data Register FCMB9_DATA $8E
Peripheral Memory Mapped Registers Table 4-38 FlexCAN Registers Address Map (Continued) (FC_BASE = $00 F800) FlexCAN is NOT available in the 56F8157 device Register Acronym Address Offset Register Description Reserved FCMB13_CONTROL $A8 Message Buffer 13 Control / Status Register FCMB13_ID_HIGH $A9 Message Buffer 13 ID High Register FCMB13_ID_LOW $AA Message Buffer 13 ID Low Register FCMB13_DATA $AB Message Buffer 13 Data Register FCMB13_DATA $AC Message Buffer 13 Data Register FCMB13_DAT
4.8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing with a default Serial Bootloader program. The Serial Bootloader application can be used to load a user application into the Program and Data Flash (NOT available in the 56F8157) memories of the device. The 56F83xx SCI/CAN Bootloader User Manual ( MC56F83xxBLUM) provides detailed information on this firmware.
Functional Description 5.3.2 Interrupt Nesting Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition SR[9]1 SR[8]1 0 0 Priorities 0, 1, 2, 3 None 0 1 Priorities 1, 2, 3 Priority 0 1 0 Priorities 2, 3 Priorities 0, 1 1 1 Priority 3 Priorities 0, 1, 2 Permitted Exceptions Masked Exceptions 1.
5.4 Block Diagram Priority Level INT1 Level 0 82->7 Priority Encoder 2->4 Decode any0 7 INT VAB CONTROL IPIC any3 Level 3 Priority Level INT82 82->7 Priority Encoder 7 IACK SR[9:8] PIC_EN 2->4 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ITCN is in this mode by default. • Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off.
Register Descriptions 5.6 Register Descriptions A register address is the sum of a base address and an address offset. The base address is defined at the system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers. Table 5-3 ITCN Register Summary (ITCN_BASE = $00 F1A0) Register Acronym Base Address + Register Name Section Location IPR0 $0 Interrupt Priority Register 0 5.6.1 IPR1 $1 Interrupt Priority Register 1 5.6.
Add.
Register Descriptions 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 15 14 Read 0 0 0 0 13 BKPT_U0IPL Write RESET 12 0 11 10 STPCNT IPL 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.
5.6.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.2.
Register Descriptions 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.
5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.6 Reserved—Bits 5–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.3.
Register Descriptions 5.6.4.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.2 GPIOE Interrupt Priority Level (GPIOE IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs.
5.6.4.5 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.6 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs.
Register Descriptions 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.
5.6.5.6 GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.7 GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
Register Descriptions 5.6.6.3 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.
5.6.6.8 SPI0 Transmitter Empty Interrupt Priority Level (SPI_XMIT IPL)— Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.7.3 Timer D, Channel 2 Interrupt Priority Level (TMRD2 IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.4 Timer D, Channel 1 Interrupt Priority Level (TMRD1 IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs.
5.6.7.8 Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.8.3 Timer B, Channel 2 Interrupt Priority Level (TMRB2 IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.8.4 Timer B, Channel 1 Interrupt Priority Level (TMRB1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs.
5.6.8.8 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.9.
5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions 5.6.10.4 Reload PWM B Interrupt Priority Level (PWMB_RL IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.10.
5.6.10.8 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.
Register Descriptions highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5. 5.6.
5.6.15.1 Reserved—Bits 15–7 This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing. 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0 This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2.
Register Descriptions 5.6.18 IRQ Pending 0 Register (IRQP0) Base + $11 15 14 13 12 11 10 Read 9 8 7 6 5 4 3 2 1 PENDING [16:2] 0 1 Write RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-20 IRQ Pending 0 Register (IRQP0) 5.6.18.1 IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.18.
5.6.20.1 IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • • 0 = IRQ pending for this vector number 1 = No IRQ pending for this vector number 5.6.21 IRQ Pending 3 Register (IRQP3) Base + $14 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING [64:49] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.
Register Descriptions 5.6.23 IRQ Pending 5 Register (IRQP5) Base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PENDING [81] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. 5.6.23.
5.6.30.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core. • • 0 = No interrupt is being sent to the 56800E core 1 = An interrupt is being sent to the 56800E core 5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new interrupt service routine.
Resets 5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0 This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait modes, it is automatically level-sensitive. • • 0 = IRQA interrupt is a low-level sensitive (default) 1 = IRQA interrupt is falling-edge sensitive 5.7 Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted.
Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features.
Operating Modes 6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and RESET operation The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the RESET pin is asserted. — COP reset and software reset operation The 56800E core and all peripherals are reset.
6.5 Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F350) Address Offset Base + $0 Base + $1 Base + $2 Base + $3 Base + $4 Base + $5 Base + $6 Base + $7 Base + $8 Address Acronym Register Name Section Location SIM_CONTROL Control Register 6.5.1 SIM_RSTSTS Reset Status Register 6.5.2 SIM_SCR0 Software Control Register 0 6.5.3 SIM_SCR1 Software Control Register 1 6.5.3 SIM_SCR2 Software Control Register 2 6.5.3 SIM_SCR3 Software Control Register 3 6.5.
Register Descriptions Add.
6.5.1.2 EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset. In addition, this pin can be used as a general purpose input pin after reset.
Register Descriptions 6.5.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.2.2 Software Reset (SWR)—Bit 5 When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.
6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (RESET pin, software reset, and COP reset). 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID) This read-only register displays the most significant half of the JTAG ID for the chip. This register reads $01F4.
Register Descriptions 6.5.6.1 Reserved—Bit 15 6.5.6.2 PWMA1—Bit 14 6.5.6.3 CAN—Bit 13 6.5.6.4 EMI_MODE—Bit 12 6.5.6.5 RESET—Bit 11 6.5.6.6 IRQ—Bit 10 6.5.6.7 XBOOT—Bit 9 6.5.6.8 PWMB—Bit 8 6.5.6.9 PWMA0—Bit 7 6.5.6.10 Reserved—Bit 6 6.5.6.11 CTRL—Bit 5 6.5.6.12 Reserved—Bit 4 6.5.6.13 JTAG—Bit 3 6.5.6.14 Reserved—Bits 2-0 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. This bit controls the pull-up resistors on the FAULTA3 pin.
The upper four bits of the GPIOB register can function as GPIO, A[23:A20], or as additional clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are programmed to operate as peripheral outputs, then the choice between A[23:A20] and additional clock outputs is done here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4] to be programmed as A[23:A20]. This can be changed by altering A[23:A20] as shown in Figure 6-9.
Register Descriptions 6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0 Selects clock to be muxed out on the CLKO pin.
GPIOC_PER Register GPIO Controlled 0 I/O Pad Control 1 SIM_ GPS Register 0 Quad Timer Controlled 1 SPI Controlled Figure 6-10 Overall Control of Pads Using SIM_GPS Control Table 6-2 Control of Pads Using SIM_GPS Control 1 GPIOC_PER GPIOC_DTR SIM_GPS Quad Timer SCRRegister OEN bits Control Registers GPIO Input 0 0 — — GPIO Output 0 1 — — Quad Timer Input / Quad Decoder Input 2 1 — 0 0 Quad Timer Output / Quad Decoder Input 3 1 — 0 1 SPI input 1 — 1 — SPI output 1 —- 1
Register Descriptions Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 3 2 1 0 C3 C2 C1 C0 0 0 0 0 Figure 6-11 GPIO Peripheral Select Register (SIM_GPS) 6.5.8.1 Reserved—Bits 15–4 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 6.5.8.2 GPIOC3 (C3)—Bit 3 This bit selects the alternate function for GPIOC3.
Base + $C Read Write RESET 15 EMI 1 14 13 12 ADCB ADCA CAN 1 1 1 11 10 DEC1 DEC0 1 1 9 8 7 TMRD TMRC TMRB 1 1 1 6 5 4 TMRA SCI 1 SCI 0 1 1 1 3 2 1 0 SPI 1 SPI 0 PWMB PWMA 1 1 1 1 Figure 6-12 Peripheral Clock Enable Register (SIM_PCE) 6.5.9.1 External Memory Interface Enable (EMI)—Bit 15 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
Register Descriptions 6.5.9.7 Quad Timer D Enable (TMRD)—Bit 9 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 Quad Timer C Enable (TMRC)—Bit 8 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.
6.5.9.15 Pulse Width Modulator B Enable (PWMB)—1 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width Modulator A Enable (PWMA)—0 Each bit controls clocks to the indicated peripheral. • • 1 = Clocks are enabled 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.
Clock Generation Overview Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Write RESET 1 0 ISAL[23:22] 1 1 Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address.
Table 6-3 Clock Operation in Power Down Modes Mode Core Clocks Peripheral Clocks Description Run Active Active Device is fully functional Wait Core and memory clocks disabled Active Peripherals are active and can produce interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications.
Resets Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those instructions, write to the SIM control register (SIM_CONTROL), described in Part 6.5.1. This procedure can be on either a permanent or temporary basis. Permanently assigned applications last only until their next reset. 6.9 Resets The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin and the Power-On Reset (POR).
7.2 Flash Access Blocking Mechanisms The 56F8357/56F8157 have several operating functional and test modes. Effective Flash security must address operating mode selection and anticipate modes in which the on-chip Flash can be compromised and read without explicit user permission. Methods to block these are outlined in the next subsections. 7.2.1 Forced Operating Mode Selection At boot time, the SIM determines in which functional modes the device will operate.
Flash Access Blocking Mechanisms The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that divides down the system clock for timed events, as illustrated in Figure 7-1. FM_CLKDIV[6] will map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz.
updated, the user must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence has completed. For details, see the JTAG Section in the 56F8300 Peripheral User Manual. Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.
Configuration Table 8-1 56F8357 GPIO Ports Configuration GPIO Port Port Width Available Pins in 56F8347 A 14 14 14 pins - EMI Address pins EMI Address B 8 8 8 pins - EMI Address pins EMI Address C 11 11 4 pins -DEC1 / TMRB / SPI1 4 pins -DEC0 / TMRA 3 pins -PWMA current sense DEC1 / TMRB DEC0 / TMRA PWMA current sense D 13 13 6 pins - EMI CSn 2 pins - SCI1 2 pins - EMI CSn 3 pins -PWMB current sense EMI Chip Selects SCI1 EMI Chip Selects PWMB current sense E 14 14 2 pins - SCI0 2
Table 8-3 GPIO External Signals Map Pins in italics are NOT available in the 56F8157 device GPIO Port GPIOA GPIOB 1This GPIO Bit Reset Function Functional Signal Package Pin 0 Peripheral A8 19 1 Peripheral A9 20 2 Peripheral A10 21 3 Peripheral A11 22 4 Peripheral A12 23 5 Peripheral A13 24 6 Peripheral A14 25 7 Peripheral A15 26 8 Peripheral A0 154 9 Peripheral A1 10 10 Peripheral A2 11 11 Peripheral A3 12 12 Peripheral A4 13 13 Peripheral A5 1
Configuration Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8157 device GPIO Port GPIOC GPIOD GPIO Bit Reset Function Functional Signal Package Pin 0 Peripheral PhaseA1 / TB0 / SCLK11 6 1 Peripheral PhaseB1 / TB1 / MOSI11 7 2 Peripheral Index1 / TB2 / MISO11 8 3 Peripheral Home1 / TB3 / SSI11 9 4 Peripheral PHASEA0 / TA0 155 5 Peripheral PHASEB0 / TA1 156 6 Peripheral Index0 / TA2 157 7 Peripheral Home0 / TA3 158 8 Periph
Table 8-3 GPIO External Signals Map (Continued) Pins in italics are NOT available in the 56F8157 device GPIO Port GPIOE GPIOF GPIO Bit Reset Function Functional Signal Package Pin 0 Peripheral TXD0 4 1 Peripheral RXD0 5 2 Peripheral A6 17 3 Peripheral A7 18 4 Peripheral SCLK0 146 5 Peripheral MOSI0 148 6 Peripheral MISO0 147 7 Peripheral SS0 145 8 Peripheral TC0 133 9 Peripheral TC1 135 10 Peripheral TD0 129 11 Peripheral TD1 130 12 Peripheral TD2 13
JTAG Information Part 9 Joint Test Action Group (JTAG) 9.1 JTAG Information Please contact your Freescale marketing device/package-specific BSDL information. representative or authorized distributor for Part 10 Specifications 10.1 General Characteristics The 56F8357/56F8157 are fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.
Note: The 56F8157 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8157 device. Table 10-1 Absolute Maximum Ratings (VSS = VSSA_ADC = 0) Characteristic Supply Voltage ADC Supply Voltage Oscillator / PLL Supply Voltage Symbol Notes VDD_IO VDDA_ADC, VREFH VREFH must be less than or equal to VDDA_ADC VDDA_OSC_PLL Min Max Unit -0.3 4.0 V -0.3 4.0 V -0.3 4.0 V VDD_CORE OCR_DIS is High -0.3 3.
General Characteristics Table 10-2 56F8357/56F8157 ElectroStatic Discharge (ESD) Protection Characteristic Min Typ Max Unit ESD for Human Body Model (HBM) 2000 — — V ESD for Machine Model (MM) 200 — — V ESD for Charge Device Model (CDM) 500 — — V Table 10-3 Thermal Characteristics6 Characteristic Comments Symbol Value Value 160-pin LQFP 160MAPBGA Unit Notes Junction to ambient Natural convection RθJA 38.5 39.90 °C/W 2 Junction to ambient (@1m/sec) RθJMA 35.4 46.
Note: The 56F8157 device is guaranteed to 40MHz and specified to meet Industrial requirements only.
DC Electrical Characteristics 10.2 DC Electrical Characteristics Note: The 56F8157 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8157 device. Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Table 10-4 Characteristic Symbol Notes Min Typ Max Unit Test Conditions Output High Voltage VOH 2.4 — — V IOH = IOHmax Output Low Voltage VOL — — 0.4 V IOL = IOLmax IIH Pin Groups 1, 2, 5, 6, 9, — 0 +/- 2.
Table 10-6 Power-On Reset Low Voltage Parameters Characteristic Symbol Min Typ Max Units POR Trip Point POR 1.75 1.8 1.9 V LVI, 2.5 volt Supply, trip point1 VEI2.5 — 2.14 — V LVI, 3.3 volt supply, trip point2 VEI3.3 — 2.7 — V Bias Current I bias — 110 130 μA 1. When VDD_CORE drops below VEI2.5, an interrupt is generated. 2. When VDD_CORE drops below VEI3.3, an interrupt is generated.
DC Electrical Characteristics Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) Mode RUN1_MAC IDD_Core IDD_IO1 IDD_ADC IDD_OSC_PLL 150mA 13μA 50mA 2.5mA Test Conditions • 60MHz Device Clock • All peripheral clocks are enabled • All peripherals running • Continuous MAC instructions with fetches from Data RAM • ADC powered on and clocked Wait3 86mA 13μA 70μA 2.
Table 10-10. PLL Parameters Characteristics Symbol Min Typical Max Unit PLL Start-up time TPS 0.3 0.5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms Min-Max Period Variation TPV 120 — 200 ps Peak-to-Peak Jitter TPJ — — 175 ps Bias Current IBIAS — 1.5 2 mA IPD — 100 150 μA Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8157 device.
AC Electrical Characteristics 10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 10-1. Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH – VIL)/2.
10.5 External Clock Operation Timing Table 10-13 External Clock Operation Timing Requirements1 Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)2 fosc 0 — 120 MHz Clock Pulse Width3 tPW 3.0 — — ns External clock input rise time4 trise — — 10 ns External clock input fall time5 tfall — — 10 ns 1. Parameters listed are guaranteed by design. 2. See Figure 10-3 for details on using the recommended connection of an external clock driver. 3.
Crystal Oscillator Timing 10.7 Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Symbol Min Typ Max Unit Crystal Start-up time TCS 4 5 10 ms Resonator Start-up time TRS 0.1 0.18 1 ms RESR — — 120 ohms Crystal Peak-to-Peak Jitter TD 70 — 250 ps Crystal Min-Max Period Variation TPV 0.12 — 1.
DCAOE and DCAEO are calculated as follows: DCAOE = 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 = 0.0 all other cases DCAEO = MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1 = 0.0 all other cases Example of DCAOE and DCAEO calculation: Assuming prescaler is set for ÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle ranges between 45% and 60% high; DCAOE = .50 - .60 = - 0.1 DCAEO = .45 - .50 = - 0.
External Memory Interface Timing Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Symbol tAWR tWR Data Out Valid to WR Asserted tDWR Wait States Configuration D M Wait States Controls Unit WWS=0 -1.477 0.50 WWS>0 -1.564 0.75 + DCAOE WWSS ns WWS=0 -0.186 0.25 + DCAOE WWS>0 -0.256 0 WWS ns WWS=0 -9.568 0.25 + DCAEO WWS=0 -1.721 0.00 WWS>0 -9.227 0.50 WWSS ns WWS>0 -1.808 0.25 + DCAOE -2.287 0.
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 Symbol Typical Min Typical Max Unit See Figure RESET Assertion to Address, Data and Control Signals High Impedance tRAZ — 21 ns 10-5 Minimum RESET Assertion Duration tRA 16T — ns 10-5 RESET Deassertion to First External Address Output3 tRDA 63T 64T ns 10-5 Edge-sensitive Interrupt Request Width tIRW 1.
Reset, Stop, Wait, Mode Select, and Interrupt Timing RESET tRA tRAZ tRDA A0–A15, D0–D15 First Fetch PS, DS, RD, WR First Fetch Figure 10-5 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 10-6 External Interrupt Timing (Negative-Edge Sensitive) A0–A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 10-7 External Level-Sensitive Interrupt Timing 56F8357 Technic
IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 10-8 Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing 10.
Serial Peripheral Interface (SPI) Timing Table 10-18 SPI Timing1 (Continued) Characteristic Symbol Data set-up time required for inputs Master Slave tDS Data hold time required for inputs Master Slave tDH Access time (time to data active from high-impedance state) Slave tA Disable time (hold time to high-impedance state) Slave tD Data Valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF Min Max Unit 20
SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tR tF Figure 10-10 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDV(ref) MOSI (Output) tDH Bits 14–1 tDI Maste
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 10-12 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD SCLK (CPOL = 1) (Input) tCL tDV tCH tR tA MISO (Output) Slave MSB out Bits 14–1 tDS tDV tDH MOSI (Input)
10.11 Quad Timer Timing Table 10-19 Timer Timing1, 2 Characteristic Symbol Min Max Unit See Figure PIN 2T + 6 — ns 10-14 Timer input high / low period PINHL 1T + 3 — ns 10-14 Timer output period POUT 1T - 3 — ns 10-14 POUTHL 0.5T - 3 — ns 10-14 Timer input period Timer output high / low period 1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns. 2. Parameters listed are guaranteed by design.
Serial Communication Interface (SCI) Timing PPH PPH PPH PPH Phase A (Input) PHL PIN PHL Phase B PHL (Input) PIN PHL Figure 10-15 Quadrature Decoder Timing 10.13 Serial Communication Interface (SCI) Timing Table 10-21 SCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-16 TXD4 Pulse Width TXDPW 0.965/BR 1.04/BR ns 10-17 Baud Rate2 1. Parameters listed are guaranteed by design. 2.
10.14 Controller Area Network (CAN) Timing Note: CAN is not available in the 56F8157 device. Table 10-22 CAN Timing1 Characteristic Baud Rate Bus Wake Up detection Symbol Min Max Unit See Figure BRCAN — 1 Mbps — T WAKEUP 5 — μs 10-18 1. Parameters listed are guaranteed by design CAN_RX CAN receive data pin (Input) T WAKEUP Figure 10-18 Bus Wakeup Detection 10.
JTAG Timing 1/fOP tPW tPW VM VM VIH TCK (Input) VIL VM = VIL + (VIH – VIL)/2 Figure 10-19 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) tDS tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 10-20 Test Access Port Timing Diagram TRST (Input) tTRST Figure 10-21 TRST Timing Diagram 56F8357 Technical Data, Rev.
10.16 Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters Characteristic Symbol Min Typ Max Unit VADIN VREFL — VREFH V Resolution RES 12 — 12 Bits Integral Non-Linearity1 INL — +/- 2.4 +/- 3.2 LSB2 Differential Non-Linearity DNL — +/- 0.7 < +1 LSB2 Input voltages Monotonicity GUARANTEED ADC internal clock fADIC 0.
Analog-to-Digital Converter (ADC) Parameters Table 10-24 ADC Parameters (Continued) Characteristic Symbol Min Typ Max Unit THD — 60.6 — db Spurious Free Dynamic Range SFDR — 61.1 — db Effective Number Of Bits8 ENOB — 9.6 — Bits Total Harmonic Distortion 1. INL measured from Vin = .1VREFH to Vin = .9VREFH 10% to 90% Input Signal Range 2. LSB = Least Significant Bit 3. ADC clock cycles 4. Assumes each voltage reference pin is bypassed with 0.1μF ceramic capacitors to ground 5.
Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDCin = 0.60V and 2.70V Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error.
Equivalent Circuit for ADC Inputs 10.17 Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample & hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to VREFH - VREFH / 2, while the other charges to the analog input voltage.
C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two of the IO cell types used on the device reveal that the power-versus-load curve does have a non-zero Y-intercept.
56F8357 Package and Pin-Out Information Part 11 Packaging Note: The 160 Map Ball Grid Array is not available in the 56F8157 device. 11.1 56F8357 Package and Pin-Out Information ANB7 ANB6 ANB5 EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VCAP2 CAN_RX CAN_TX VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 TD3 TD2 TD1 TD0 ISA2 ISA1 ISA0 VSS EXTBOOT VSS This section contains package and pin-out information for the 56F8357.
Table 11-1 56F8357 160-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8357 Package and Pin-Out Information Table 11-1 56F8357 160-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 D12 D11 SCLK0 VPP1 TMS TC0 TD1 ISA0 ANB7 ANB5 ANB4 D13 MOSI0 CAN_RX TDI TC1 TD0 EXTBOOT ANB6 ANB3 ANB1 A INDEX0 PHASEA0 B TXD0 EMI_ HOME0 PHASEB0 MODE C PHASEA1 VPP2 A0 D14 PHASEB1 RXD0 CLKO MISO0 SS0 CAN_TX TDO TCK TRST TD2 A1 A2 VDD_IO VSS VSS VCAP2 VDD_IO TD3 ISA1 D ANB2 ANB0 VDDA_ADC ISA2 VSSA_ADC VREFP VREFH E HOME1 INDEX1 TEMP_ VREFLO SENSE ANA7 VREFMID F A4 A3 A5 VDD_IO VDD_IO ANA4 ANA3 VREF
56F8357 Package and Pin-Out Information Table 11-2 56F8357 -160 MAPBGA Package Identification by Pin Number Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No.
Table 11-2 56F8357 -160 MAPBGA Package Identification by Pin Number (Continued) Ball No. Signal Name Ball No. Signal Name Ball No. Signal Name Ball No.
56F8357 Package and Pin-Out Information D X LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA Y M K NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. E MILLIMETERS DIM MIN MAX A 1.32 1.
11.2 56F8157 Package and Pin-Out Information ANB7 ANB6 ANB5 VCAP2 NC NC VPP1 TDO TDI TMS TCK TRST TC1 VDD_IO TC0 GPIOE13 GPIOE12 GPIOE11 GPIOE10 GPIOC10 GPIOC9 GPIOC8 VSS EXTBOOT EMI_MODE HOME0 INDEX0 PHASEB0 PHASEA0 A0 D15 D14 D13 D12 D11 MOSI0 MISO0 SCLK0 SS0 VSS This section contains package and pin-out information for the 56F8157. This device comes in a 160-pin Low-profile Quad Flat Pack (LQFP).
56F8157 Package and Pin-Out Information Table 11-3 56F8157 160-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 11-3 56F8157 160-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
56F8157 Package and Pin-Out Information 160X 0.20 C A-B D D D 2 b GG c1 D c 6 SECTION G-G E 2 E1 2 E E1 B A (b) D1 2 D1 4X 0.20 H A-B D DETAIL F 0.08 C e e/2 156X C 4X SEATING PLANE 160X e 0.08 M C A-B D θ1 R1 R2 A2 A θ2 θ3 A1 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED WHERE THE LEADS EXIT THE PLASTIC BODY AT DATUM PLANE H. 4.
Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJΑ x PD) where: TA = Ambient temperature for the package (oC) RθJΑ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
Electrical Design Considerations The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
Power Distribution and I/O Ring Implementation Part 13 Ordering Information Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 13-1 Ordering Information Pin Count Frequency (MHz) Ambient Temperature Range Order Number Low-Profile Quad Flat Pack (LQFP) 160 60 -40° to + 105° C MC56F8357VPY60 3.0–3.
56F8357 Technical Data, Rev.
Power Distribution and I/O Ring Implementation 56F8357 Technical Data, Rev.
56F8357 Technical Data, Rev.
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