Datasheet

56F8357 Technical Data, Rev. 15
112 Freescale Semiconductor
Preliminary
6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F4.
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$601D.
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6 SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
Base + $6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
Write
RESET
0 0 0 0 0 0 01111 1 0100
Base + $7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1
Write
RESET
0 1 1 0 0 0 00000 1 1101
Base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0
PWMA1 CAN
EMI_
MODE
RESET
IRQ XBOOT PWMB PWMA0
0
CTRL
0
JTAG
000
Write
RESET
0000 000 0 0 0000000