Datasheet

56F8357 Technical Data, Rev. 15

Freescale Semiconductor 117

Preliminary

Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)

6.5.8.1 Reserved—Bits 15–4

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.8.2 GPIOC3 (C3)—Bit 3

This bit selects the alternate function for GPIOC3.

• 0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the

56F8300 Peripheral User Manual)

• 1 = SS1

6.5.8.3 GPIOC2 (C2)—Bit 2

This bit selects the alternate function for GPIOC2.

• 0 = INDEX1/TB2 (default)

•1 = MISO1

6.5.8.4 GPIOC1 (C1)—Bit 1

This bit selects the alternate function for GPIOC1.

• 0 = PHASEB1/TB1 (default)

•1 = MOSI1

6.5.8.5 GPIOC0 (C0)—Bit 0

This bit selects the alternate function for GPIOC0.

• 0 = PHASEA1/TB0 (default)

• 1 = SCLK1

6.5.9 Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used enable or disable clocks to the peripherals as a power savings

feature. The clocks can be individually controlled for each peripheral on the chip.

Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

0 0 0 0 0 0 0 0 0 0 0 0

C3 C2 C1 C0

Write

RESET

000000000000 0 0 0 0