Datasheet

Architecture Block Diagram
56F8357 Technical Data, Rev. 15
Freescale Semiconductor 13
Preliminary
Figure 1-2 Peripheral Subsystem
IPBus
Timer A
Timer C
SPI 1
ADCB
ADCA
FlexCAN
GPIO A
SPI 0
SCI 0
SCI 1
Interrupt
Controller
To/From IPBus Bridge
PWMA
PWMB
COP
RESET
Quadrature Decoder 0
Note: ADC A and ADC B use the same volt-
age reference circuit with V
REFH
, V
REFP
,
V
REFMID
, V
REFN
, and V
REFLO
pins.
GPIO B
GPIO C
GPIO D
GPIO E
GPIO F
Timer B
Quadrature Decoder 1
TEMP_SENSE
CLKGEN
(OSC/PLL)
POR & LVI
SIM
SYNC Output
SYNC Output
Timer D
NOT available on the 56F8157 device.
Low Voltage Interrupt
System POR
COP Reset
ch3i ch2i
ch3o ch2o
2
13
13
2
8
8
1
2
2
4
4
4
4