Datasheet

56F8357 Technical Data, Rev. 15
152 Freescale Semiconductor
Preliminary
10.14 Controller Area Network (CAN) Timing
Note: CAN is not available in the 56F8157 device.
Figure 10-18 Bus Wakeup Detection
10.15 JTAG Timing
Table 10-22 CAN Timing
1
1. Parameters listed are guaranteed by design
Characteristic Symbol Min Max Unit See Figure
Baud Rate
BR
CAN
—
1 Mbps
—
Bus Wake Up detection
T
WAKEUP
5
—
μs 10-18
Table 10-23 JTAG Timing
Characteristic Symbol Min Max Unit See Figure
TCK frequency of operation
using EOnCE
1
1. TCK frequency of operation must be less than 1/8 the processor rate.
f
OP
DC SYS_CLK/8 MHz 10-19
TCK frequency of operation not
using EOnCE
1
f
OP
DC SYS_CLK/4 MHz 10-19
TCK clock pulse width
t
PW
50 — ns 10-19
TMS, TDI data set-up time
t
DS
5—ns 10-20
TMS, TDI data hold time
t
DH
5—ns 10-20
TCK low to TDO data valid
t
DV
—30ns 10-20
TCK low to TDO tri-state
t
TS
—30ns 10-20
TRST
assertion time
t
TRST
2T
2
2. T = processor clock period (nominally 1/60MHz)
—ns 10-21
T
WAKEUP
CAN_RX
CAN receive
data pin
(Input)