Datasheet

56F8357 Technical Data, Rev. 15
18 Freescale Semiconductor
Preliminary
Figure 2-2 56F8157 Signals Identified by Functional Group
1
(160-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
V
DD_IO
V
DDA_OSC_PLL
V
DDA_ADC
V
SS
V
SSA_ADC
Other
Supply
Ports
PLL
and
Clock
External
Address
Bus
or GPIO
External
Data
Bus
SCI 0 or
GPIO
SCI 1
or GPIO
1
1
7
1
6
V
PP
1 & V
PP
2
2
Power
Ground
Power
Ground
A8 - A15 (GPIOA0 - 7)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
TXD1 (GPIOD6)
RXD1 (GPIOD7)
TCK
TMS
TDI
TDO
TRST
Quadrature
Decoder 0
or Quad
Timer A
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
(MOSI1, GPIOC1)
(MISO1, GPIOC2)
(S
S1, GPIOC3)
(GPIOC8 - 10)
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
PWMB0 - 5
ANA0 - 7
ANB0 - 7
V
REF
TC0 - 1 (GPIOE8 - 9)
(GPIOE10 - 13)
IRQA
IRQB
RESET
RSTO
SPI0 or
GPIO
GPIO
SPI 1 or
GPIO
PWMB
ADCB
ADCA
Quad
Timer C or
GPIO
INTERRUPT/
PROGRAM
CONTROL
(SCLK1, GPIOC0)
8
GPIOB0 - 3 (A16 - 19)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
6
3
4
8
5
8
2
4
1
1
1
1
1
56F8157
EXTAL
XTAL
CLKO
1
1
1
V
CAP
1 - V
CAP
4
4
A0 - A5 (GPIOA8 - 13)
6
A6 - A7 (GPIOE2 - 3)
2
RD
1
WR
1
PS / CS0 (GPIODF8)
1
DS / CS1 (GPIOFD9)
1
GPIOD0 - 5 (CS2 - 7)
6
JTAG/
EOnCE
Port
External
Bus
Control
D7 - D15 (GPIOF0 - 8)
9
D0 - D6 (GPIOF9 - 15)
7
EXTBOOT
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0
(GPIOE7)
1
1
1
SCLK0 (GPIOE4)
1
1
EMI_MODE
Power
CLKMODE
1
OCR_DIS
1
1
GPIOB4 (A20, prescaler_clock)
1
GPIOB5 (A21, SYS_CLK)
1
GPIOB6 (A22, SYS_CLK2)
1
GPIOB7 (A23, oscillator_clock)
4
* When the on-chip regulator is disabled, these
four pins become 2.5V V
DD_CORE
.