Datasheet

Signal Pins
56F8357 Technical Data, Rev. 15
Freescale Semiconductor 19
Preliminary
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Note: Signals in italics are NOT available in the 56F8157 device.
Note: The 160 Map Ball Grid Array is not available in the 56F8157 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Note: LQFP Pin numbers and MBGA Ball numbers do not always correlate in Table 2-2. Please contact
factory for exact correlation.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
Pin
No.
Ball No. Type
State
During
Reset
Signal Description
V
DD_IO
1 F4 Supply I/O Power — This pin supplies 3.3V power to the chip I/O
interface and also the Processor core throught the on-chip
voltage regulator, if it is enabled.
V
DD_IO
16 K5
V
DD_IO
31 E5
V
DD_IO
42 K7
V
DD_IO
77 E9
V
DD_IO
96 K10
V
DD_IO
134 F11
V
DDA_ADC
114 C14 Supply ADC Power — This pin supplies 3.3V power to the ADC
modules. It must be connected to a clean analog power
supply.
V
DDA_OSC_
PLL
92 K13 Supply Oscillator and PLL Power — This pin supplies 3.3V power to
the OSC and to the internal regulator that in turn supplies the
Phase Locked Loop. It must be connected to a clean analog
power supply.