Datasheet

Signal Pins
56F8357 Technical Data, Rev. 15
Freescale Semiconductor 25
Preliminary
D7
(GPIOF0)
28 K1 Input/
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Bus — D7 - D14 specify part of the data for external
program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), D7 - D15and EMI control signals are tri-stated
when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
Port F GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to data bus functionality.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
D8
(GPIOF1)
29 K3
D9
(GPIOF2)
30 K2
D10
(GPIOF3)
32 K4
D11
(GPIOF4)
149 A5
D12
(GPIOF5)
150 A4
D13
(GPIOF6)
151 B5
D14
(GPIOF7)
152 C4
D15
(GPIOF8)
153 A3
RD
52 P5 Output In reset,
output is
disabled,
pull-up is
enabled
Read Enable — RD
is asserted during external memory read
cycles. When RD
is asserted low, pins D0 - D15 become
inputs and an external device is enabled onto the data bus.
When RD
is deasserted high, the external data is latched
inside the device. When RD
is asserted, it qualifies the A0 -
A23, PS
, DS, and CSn pins. RD can be connected directly to
the OE
pin of a static RAM or ROM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), RD
is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in
the SIM_PUDR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
Pin
No.
Ball No. Type
State
During
Reset
Signal Description