Datasheet

56F8357 Technical Data, Rev. 15
26 Freescale Semiconductor
Preliminary
WR
51 L4 Output In reset,
output is
disabled,
pull-up is
enabled
Write Enable — WR
is asserted during external memory write
cycles. When WR
is asserted low, pins D0 - D15 become
outputs and the device puts data on the bus. When WR is
deasserted high, the external data is latched inside the
external device. When WR
is asserted, it qualifies the A0 -
A23, PS, DS, and CSn pins. WR can be connected directly to
the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR
is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in
the SIM_PUDR register.
PS
(CS0)
(GPIOD8)
53 N6 Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Program Memory Select — This signal is actually CS0 in the
EMI, which is programmed at reset for compatibility with the
56F80x PS signal. PS is asserted low for external program
memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS0
is tri-stated when the external bus is inactive.
CS0 resets to provide the PS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
DS
(CS1)
(GPIOD9)
54 L5 Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Memory Select — This signal is actually CS1
in the EMI,
which is programmed at reset for compatibility with the 56F80x
DS
signal. DS is asserted low for external data memory
access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS1
is tri-stated when the external bus is inactive.
CS1
resets to provide the DS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
Pin
No.
Ball No. Type
State
During
Reset
Signal Description