Datasheet

56F8357 Technical Data, Rev. 15
46 Freescale Semiconductor
Preliminary
4.4 Data Map
Note: Data Flash is NOT available on the 56F8157 device.
ADCA 74 0-2 P:$94 ADC A Conversion Complete / End of Scan
ADCB 75 0-2 P:$96 ADC B Zero Crossing or Limit Error
ADCA 76 0-2 P:$98 ADC A Zero Crossing or Limit Error
PWMB 77 0-2 P:$9A Reload PWM B
PWMA 78 0-2 P:$9C Reload PWM A
PWMB 79 0-2 P:$9E PWM B Fault
PWMA 80 0-2 P:$A0 PWM A Fault
core 81 - 1 P:$A2 SW Interrupt LP
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are
the chip reset addresses; therefore, these locations are not interrupt vectors.
2.
Table 4-6 Data Memory Map
1
1. All addresses are 16-bit Word addresses, not byte addresses.
Begin/End
Address
EX = 0
2
2. In the Operating Mode Register (OMR).
EX = 1
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 3000
External Memory External Memory
X:$00 2FFF
X:$00 2000
On-Chip Data Flash
8KB
X:$00 1FFF
X:$00 0000
On-Chip Data RAM
16KB
3
3. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle, long-word operations.
Table 4-5 Interrupt Vector Table Contents
1
(Continued)
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function