Datasheet

56F8357 Technical Data, Rev. 15

50 Freescale Semiconductor

Preliminary

SPI #0 SPI0 X:$00 F2A0 4-25

SPI #1 SPI1 X:$00 F2B0 4-26

COP COP X:$00 F2C0 4-27

PLL, OSC CLKGEN X:$00 F2D0 4-28

GPIO Port A GPIOA X:$00 F2E0 4-29

GPIO Port B GPIOB X:$00 F300 4-30

GPIO Port C GPIOC X:$00 F310 4-31

GPIO Port D GPIOD X:$00 F320 4-32

GPIO Port E GPIOE X:$00 F330 4-33

GPIO Port F GPIOF X:$00 F340 4-34

SIM SIM X:$00 F350 4-35

Power Supervisor LVI X:$00 F360 4-36

FM FM X:$00 F400 4-37

FlexCAN FC X:$00 F800 4-38

Table 4-10 External Memory Integration Registers Address Map

(EMI_BASE = $00 F020)

CSBAR 0 $0

Chip Select Base Address Register 0 0x0004 = 64K when

EXT_BOOT = 0 or EMI_MODE = 0

0x0008 = 1M when EMI_MODE = 1

(Selects entire program space for

CS0)

CSBAR 1 $1

Chip Select Base Address Register 1 0x0004 = 64K when

EMI_MODE = 0

0x0008 = 1M when EMI_MODE = 1

(Selects A0-A19 addressable data

space for CS1)

CSBAR 2 $2

Chip Select Base Address Register 2

CSBAR 3 $3

Chip Select Base Address Register 3

CSBAR 4 $4

Chip Select Base Address Register 4

CSBAR 5 $5

Chip Select Base Address Register 5

CSBAR 6 $6

Chip Select Base Address Register 6

CSBAR 7 $7

Chip Select Base Address Register 7

Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued)

Peripheral Prefix Base Address Table Number