Datasheet

Peripheral Memory Mapped Registers

56F8357 Technical Data, Rev. 15

Freescale Semiconductor 57

Preliminary

TMRD1_COMSCR $1A Comparator Status and Control Register

Reserved

TMRD2_CMP1 $20 Compare Register 1

TMRD2_CMP2 $21 Compare Register 2

TMRD2_CAP $22 Capture Register

TMRD2_LOAD $23 Load Register

TMRD2_HOLD $24 Hold Register

TMRD2_CNTR $25 Counter Register

TMRD2_CTRL $26 Control Register

TMRD2_SCR $27 Status and Control Register

TMRD2_CMPLD1 $28 Comparator Load Register 1

TMRD2_CMPLD2 $29 Comparator Load Register 2

TMRD2_COMSCR $2A Comparator Status and Control Register

Reserved

TMRD3_CMP1 $30 Compare Register 1

TMRD3_CMP2 $31 Compare Register 2

TMRD3_CAP $32 Capture Register

TMRD3_LOAD $33 Load Register

TMRD3_HOLD $34 Hold Register

TMRD3_CNTR $35 Counter Register

TMRD3_CTRL $36 Control Register

TMRD3_SCR $37 Status and Control Register

TMRD3_CMPLD1 $38 Comparator Load Register 1

TMRD3_CMPLD2 $39 Comparator Load Register 2

TMRD3_COMSCR $3A Comparator Status and Control Register

Table 4-14 Quad Timer D Registers Address Map (Continued)

(TMRD_BASE = $00 F100)

Quad Timer D is NOT available in the 56F8157 device