Datasheet

Peripheral Memory Mapped Registers

56F8357 Technical Data, Rev. 15

Freescale Semiconductor 59

Preliminary

PWMB_PWMVAL1 $7 Value Register 1

PWMB_PWMVAL2 $8 Value Register 2

PWMB_PWMVAL3 $9 Value Register 3

PWMB_PWMVAL4 $A Value Register 4

PWMB_PWMVAL5 $B Value Register 5

PWMB_PMDEADTM $C Dead Time Register

PWMB_PMDISMAP1 $D Disable Mapping Register 1

PWMB_PMDISMAP2 $E Disable Mapping Register 2

PWMB_PMCFG $F Configure Register

PWMB_PMCCR $10 Channel Control Register

PWMB_PMPORT $11 Port Register

PWMB_PMICCR $12

PWM Internal Correction Control Register

Table 4-17 Quadrature Decoder 0 Registers Address Map

(DEC0_BASE = $00 F180)

DEC0_DECCR $0 Decoder Control Register

DEC0_FIR $1 Filter Interval Register

DEC0_WTR $2 Watchdog Time-out Register

DEC0_POSD $3 Position Difference Counter Register

DEC0_POSDH $4 Position Difference Counter Hold Register

DEC0_REV $5 Revolution Counter Register

DEC0_REVH $6 Revolution Hold Register

DEC0_UPOS $7 Upper Position Counter Register

DEC0_LPOS $8 Lower Position Counter Register

DEC0_UPOSH $9 Upper Position Hold Register

DEC0_LPOSH $A Lower Position Hold Register

DEC0_UIR $B Upper Initialization Register

DEC0_LIR $C Lower Initialization Register

DEC0_IMR $D Input Monitor Register

Table 4-16 Pulse Width Modulator B Registers Address Map (Continued)

(PWMB_BASE = $00 F160)