Datasheet

56F8365 Technical Data, Rev. 9
104 Freescale Semiconductor
5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)
Figure 5-19 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.17.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.18 IRQ Pending 0 Register (IRQP0)
Figure 5-20 IRQ Pending 0 Register (IRQP0)
5.6.18.1 IRQ Pending (PENDING)—Bits 16–2
This register combines with the other five to represent the pending IRQs for interrupt vector numbers two
through 81.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.18.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.19 IRQ Pending 1 Register (IRQP1)
Figure 5-21 IRQ Pending 1 Register (IRQP1)
Base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 1
VECTOR ADDRESS HIGH
Write
RESET
0000000000000000
Base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING [16:2] 1
Write
RESET
1111111111111111
$Base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING [32:17]
Write
RESET
1111111111111111