Datasheet

56F8365 Technical Data, Rev. 9
108 Freescale Semiconductor
5.6.30.6 IRQB State Pin (IRQB STATE)—Bit 3
This read-only bit reflects the state of the external IRQB pin.
5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8 IRQB Edge Pin (IRQB Edg)—Bit 1
This bit controls whether the external IRQB interrupt is edge or level sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•0 = IRQB interrupt is a low-level sensitive (default)
•1 = IRQB
interrupt is falling-edge sensitive.
5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0
This bit controls whether the external IRQA interrupt is edge or level sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•0 = IRQA interrupt is a low-level sensitive (default)
•1 = IRQA
interrupt is falling-edge sensitive.
5.6.31 Reserved—Base + $1E
5.6.32 Interrupt Priority Register 10 (IPR10)
Figure 5-27 Interrupt Priority Register 10 (IPR10)
Note: This register is NOT available in the 56F8165 device.
5.6.32.1 Reserved—Bits 15 - 8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.32.2 FlexCAN2 Message Buffer Interrupt Priority Level
(FlexCAN2_MSGBUF IPL)—Bits 7 - 6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
Base + $1F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0
FLEXCAN2_
MSGBUF IPL
FLEXCAN2_
WKUP IPL
FLEXCAN2_
ERR IPL
FLEXCAN2_
BOFF IPL
Write
RESET
0001000000000000