Datasheet

Architecture Block Diagram
56F8365 Technical Data, Rev. 9
Freescale Semiconductor 11
Figure 1-1 System Bus Interfaces
Note: Flash memories are encapsulated within the Flash Memory (FM) Module. Flash control is
accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed
between the core and the Flash memories.
Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits.
56800E
Program
Flash
Program
RAM
Data RAM
EMI*
IPBus
Bridge
Boot
Flash
Flash
Memory
Module
* EMI not functional in this package; since only part of
the address/data bus is bonded out, use as GPIO pins
JTAG / EOnCE
5
CHIP
TAP
Controller
TAP
Linking
Module
External
JTAG
Port
pdb_m[15:0]
pab[20:0]
cdbw[31:0]
xab1[23:0]
xab2[23:0]
cdbr_m[31:0]
xdb2_m[15:0]
11
4
6
To Flash
Control Logic
IPBus
Address
Data
Control
Data
Flash
NOT available on the 56F8165 device.