Datasheet

56F8365 Technical Data, Rev. 9
112 Freescale Semiconductor
The reset state for MB and MA will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed
information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For
additional information on the EX bit, see Part 4.4. For all other bits, see the DSP56F800E Reference
Manual.
Note: The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
6.5 Register Descriptions
Table 6-1 SIM Registers (SIM_BASE = $00 F350)
Address Offset Address Acronym Register Name Section Location
Base + $0 SIM_CONTROL Control Register 6.5.1
Base + $1 SIM_RSTSTS Reset Status Register 6.5.2
Base + $2 SIM_SCR0 Software Control Register 0 6.5.3
Base + $3 SIM_SCR1 Software Control Register 1 6.5.3
Base + $4 SIM_SCR2 Software Control Register 2 6.5.3
Base + $5 SIM_SCR3 Software Control Register 3 6.5.3
Base + $6 SIM_MSH_ID Most Significant Half of JTAG ID 6.5.4
Base + $7 SIM_LSH_ID Least Significant Half of JTAG ID 6.5.5
Base + $8 SIM_PUDR Pull-up Disable Register 6.5.6
Reserved
Base + $A SIM_CLKOSR CLKO Select Register 6.5.7
Base + $B SIM_GPS GPIO Peripheral Select Register 6.5.8
Base + $C SIM_PCE Peripheral Clock Enable Register 6.5.9
Base + $D SIM_ISALH I/O Short Address Location High Register 6.5.10
Base + $E SIM_ISALL I/O Short Address Location Low Register 6.5.10
Base + $F SIM_PCE2 Peripheral Clock Enable Register 2 6.5.11