Datasheet

56F8365 Technical Data, Rev. 9
116 Freescale Semiconductor
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$D01D.
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6 SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1 Reserved—Bit 15
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2 PWMA1—Bit 14
This bit controls the pull-up resistors on the FAULTA3 pin.
Base + $6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 1110 1 0110
Write
RESET
0 0 0 0 0 0 0 1110 1 0110
Base + $7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
1 1 0 1 0 0 0 0000 1 1101
Write
RESET
1 1 0 1 0 0 0 0000 1 1101
Base + $8
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0
PWMA1 CAN
EMI_
MODE
RESET
IRQ XBOOT PWMB PWMA0
0
CTRL
0
JTAG
000
Write
RESET
0000 000 0 0 0000000