Datasheet

56F8365 Technical Data, Rev. 9

Freescale Semiconductor 121

Figure 6-11 Overall Control of GPIOD Pads Using SIM_GPS Control

Figure 6-12 GPIO Peripheral Select Register (SIM_GPS)

6.5.8.1 Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

Table 6-3 Control of GPIOD Pads Using SIM_GPS Control

1. This applies to the two pins that serve as EMI CSn / CAN2 / GPIOD functions. A separate set of control

bits is used for each pin.

Pin Function

Control Registers

Comments

GPIOD_PER

GPIOD_DDR

SIM_GPS

GPIO Input 0 0 —

GPIO Output 0 1 —

EMI I/O 1 — 0 EMI CSn

pins are always outputs

CAN2 1 — 1 CAN2_TX is always an output

CAN2_RX is always an input

Base + $B 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Read

0 0 0 0 0 0 0 0 0 0

D1 D0 C3 C2 C1 C0

Write

RESET

000000000000 0 0 0 0

GPIOD_PER Register

GPIO Controlled

I/O

Pad Control

SIM_

GPS Register

EMI Controlled

CAN2 Controlled