Datasheet

56F8365 Technical Data, Rev. 9
126 Freescale Semiconductor
Note: The pipeline delay between setting this register set and using short I/O addressing with the new value
is three cycles.
Figure 6-15 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Figure 6-16 I/O Short Address Location Low Register (SIM_ISAL)
6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.5.11 Peripheral Clock Enable Register 2 (SIM_PCE2)
The Peripheral Clock Enable Register 2 is used to enable or disable clocks to the peripherals as a
power-saving feaure. The clocks can be individually controller for each peripheral on the chip.
6.5.11.1 Reserved—Bits 15–1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.11.2 CAN2 Enable—Bit 0
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
1 1 1 1 1 1 1 1 1 1 1 1 1 1
ISAL[23:22]
Write
RESET
1111111 11111 1 1 11
Base + $E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
ISAL[21:6]
Write
RESET
1111111 11111 1 1 11
Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CAN
2
Write
RESET
0000000 00000 0 0 01