Datasheet

External Clock Operation Timing
56F8365 Technical Data, Rev. 9
Freescale Semiconductor 149
10.5 External Clock Operation Timing
Figure 10-4 External Clock Timing
10.6 Phase Locked Loop Timing
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash
module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
Table 10-13 External Clock Operation Timing Requirements
1
1. Parameters listed are guaranteed by design.
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)
2
2. See Figure 10-4 for details on using the recommended connection of an external clock driver.
f
osc
0—120MHz
Clock Pulse Width
3
3. The high or low pulse width must be no smaller than 8.0ns or the chip will not function.
t
PW
3.0 — — ns
External clock input rise time
4
4. External clock input rise time is measured from 10% to 90%.
t
rise
— — 10 ns
External clock input fall time
5
5. External clock input fall time is measured from 90% to 10%.
t
fall
— — 10 ns
Table 10-14 PLL Timing
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
f
osc
488.4MHz
PLL output frequency
2
(f
OUT
)
f
op
160 — 260 MHz
PLL stabilization time
3
-40 to +125C
t
plls
—110ms
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
t
fall
t
rise