Datasheet

Introduction
56F8365 Technical Data, Rev. 9
Freescale Semiconductor 15
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins in Package
56F8365 56F8165
Power (V
DD
or V
DDA
)99
Power Option Control 1 1
Ground (V
SS
or V
SSA
)66
Supply Capacitors
1
& V
PP
1. If the on-chip regulator is disabled, the V
CAP
pins serve as 2.5V V
DD_CORE
power inputs
66
PLL and Clock 4 4
Bus Control 6 6
Interrupt and Program Control 4 4
Pulse Width Modulator (PWM) Ports 26 13
Serial Peripheral Interface (SPI) Port 0 4 4
Serial Peripheral Interface (SPI) Port 1 — 4
Quadrature Decoder Port 0
2
2. Alternately, can function as Quad Timer pins or GPIO
44
Quadrature Decoder Port 1
3
3. Pins in this section can function as Quad Timer, SPI 1, orGPIO
4—
Serial Communications Interface (SCI) Ports 4 4
CAN Ports 2 —
Analog-to-Digital Converter (ADC) Ports 21 21
Timer Module Ports 6 4
JTAG/Enhanced On-Chip Emulation (EOnCE) 5 5
Temperature Sense 1 —
Dedicated GPIO ( Address Bus = 11; Data Bus = 4
4
)
4. EMI not functional in these packages; use as GPIO pins.
Note: See Table 1-1 for 56F8165 functional differences.
28 28