Datasheet

56F8365 Technical Data, Rev. 9
150 Freescale Semiconductor
10.7 Crystal Oscillator Timing
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
OUT
/2), please refer to the OCCS chapter in
the 56F8300 Peripheral User Manual.
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
Table 10-15 Crystal Oscillator Parameters
Characteristic Symbol Min Typ Max Unit
Crystal Start-up time T
CS
4510ms
Resonator Start-up time T
RS
0.1 0.18 1 ms
Crystal ESR R
ESR
——120ohms
Crystal Peak-to-Peak Jitter T
D
70 — 250 ps
Crystal Min-Max Period Variation T
PV
0.12 — 1.5 ns
Resonator Peak-to-Peak Jitter T
RJ
——300ps
Resonator Min-Max Period Variation T
RP
——300ps
Bias Current, high-drive mode I
BIASH
—250290A
Bias Current, low-drive mode I
BIASL
—80110A
Quiescent Current, power-down mode I
PD
—0 1A
Table 10-16 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
Characteristic Symbol
Typical
Min
Typical
Max
Unit See Figure
Minimum RESET
Assertion Duration
t
RA
16T — ns 10-5
Edge-sensitive Interrupt Request Width
t
IRW
1.5T — ns 10-6
IRQA
, IRQB Assertion to General Purpose
Output Valid, caused by first instruction
execution in the interrupt service routine
t
IG
18T — ns 10-7
t
IG
- FAST 14T —