Datasheet

56F8365 Technical Data, Rev. 9
158 Freescale Semiconductor
Figure 10-15 Quadrature Decoder Timing
10.12 Serial Communication Interface (SCI) Timing
Figure 10-16 RXD Pulse Width
Table 10-20 SCI Timing
1
1. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Baud Rate
2
2. f
MAX
is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8365 device and
40MHz for the 56F8165 device.
BR
—
(f
MAX
/16) Mbps
—
RXD
3
Pulse Width
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXD
PW
0.965/BR 1.04/BR ns 10-16
TXD
4
Pulse Width
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
TXD
PW
0.965/BR 1.04/BR ns 10-17
Phase B
(Input)
P
IN
P
HL
P
HL
Phase A
(Input)
P
IN
P
HL
P
HL
P
PH
P
PH
P
PH
P
PH
RXD
PW
RXD
SCI receive
data pin
(Input)