Datasheet

56F8365 Technical Data, Rev. 9
162 Freescale Semiconductor
Uncalibrated Offset Voltage V
OFFSET
— +/- 27 +/- 40 mV
Calibrated Absolute Error
6
AE
CAL
— See Figure 10-22 —LSBs
Calibration Factor 1
7
CF1 — — 0.002289 —
Calibration Factor 2
7
CF2 — — –25.6 —
Crosstalk between channels — — –60 — dB
Common Mode Voltage V
common
—(V
REFH
- V
REFLO
) / 2 — V
Signal-to-noise ratio SNR — 64.6 — db
Signal-to-noise plus distortion ratio SINAD — 59.1 — db
Total Harmonic Distortion THD — 60.6 — db
Spurious Free Dynamic Range SFDR — 61.1 — db
Effective Number Of Bits
8
ENOB — 9.6 — Bits
Non-averaged DC drift of error over
temperature from 27 C
9
—— — 3 LSB
1. INL measured from V
in
= .1V
REFH
to V
in
= .9V
REFH
10% to 90% Input Signal Range
2. LSB = Least Significant Bit
3. ADC clock cycles
4. Assumes each voltage reference pin is bypassed with 0.1F ceramic capacitors to ground
5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of
the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.
6. Absolute error includes the effects of both gain error and offset error.
7. Please see the 56F8300Peripheral User’s Manual for additional information on ADC calibration.
8. ENOB = (SINAD - 1.76)/6.02
9. Temperature range –40 C to 150 C
Table 10-23 ADC Parameters (Continued)
Characteristic Symbol Min Typ Max Unit