Datasheet

56F8365 Technical Data, Rev. 9
22 Freescale Semiconductor
D7
(GPIOF0)
22 Input/
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Bus — D7 - D10 specify part of the data for external
program or data memory accesses. Depending upon the state of
the DRV bit in the SEMI bus control register (BCR), D7 - D10 are
tri-stated when the external bus is inactive
Port F GPIO — These four GPIO pins can be individually
programmed as input or output pins.
After reset, these pins default to Data Bus functionality and should
be programmed as GPIO.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
D8
(GPIOF1)
23
D9
(GPIOF2)
24
D10
(GPIOF3)
26
GPIOD0
(CS2
)
(CAN2_TX)
42 Input/
Output
Output
Open
Drain
Output
Input,
pull-up
enabled
Port D GPIO — This GPIO pin can be individually programmed
as an input or output pin.
Chip Select — CS2 may be programmed within the EMI module
to act as a chip select for specific areas of the external memory
map. Depending upon the state of the DRV bit in the EMI Bus
Control Register (BCR),CS2
is tri-stated when the external bus is
inactive.
FlexCAN2 Transmit Data — CAN output.
At reset, this pin is configured as GPIO. This configuration can be
changed by setting bit 0 in the GPIO_D_PER register, then
change bit 4 in the SIM_GPS register to select the desired
peripheral function.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal
Name
Pin No. Type
State
During
Reset
Signal Description