Datasheet

56F8365 Technical Data, Rev. 9
44 Freescale Semiconductor
4.4 Data Map
Note: Data Flash is NOT available on the 56F8165 device.
PWMB 79 0-2 P:$9E PWM B Fault
PWMA 80 0-2 P:$A0 PWM A Fault
core 81 - 1 P:$A2 SW Interrupt LP
FLEXCAN2 82 0-2 P:$A4 FlexCAN Bus-Off
FLEXCAN2 83 0-2 P:$A6 FlexCAN Error
FLEXCAN2 84 0-2 P:$A8 FlexCAN Wake Up
FLEXCAN2 85 0-2 P:$AA FlexCAN Message Buffer Interrupt
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0400 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are
the chip reset addresses; therefore, these locations are not interrupt vectors.
Table 4-6 Data Memory Map
1, 2
1. Information in shaded areas not applicable to 56F8365/56F8165.
2. All addresses are 16-bit Word addresses, not byte addresses.
Begin/End
Address
EX = 0
3
3. In the Operating Mode Register
EX = 1
4
4. Setting EX = 1 is not recommended in the 56F8365/56F8165, since the EMI is not functional in this package.
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 8000
External Memory
External Memory
X:$00 7FFF
X:$00 4000
On-Chip Data Flash
32KB
X:$003FFF
X:$00 0000
On-Chip Data RAM
32KB
5
5. The Data RAM is organized as an 8K x 32-bit memory to allow single-cycle, long-word operations.
Table 4-5 Interrupt Vector Table Contents
1
(Continued)
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function