Datasheet

Peripheral Memory Mapped Registers

56F8365 Technical Data, Rev. 9

Freescale Semiconductor 53

TMRB3_CMPLD1 $38 Comparator Load Register 1

TMRB3_CMPLD2 $39 Comparator Load Register 2

TMRB3_COMSCR $3A Comparator Status and Control Register

Table 4-13 Quad Timer C Registers Address Map

(TMRC_BASE = $00 F0C0)

TMRC0_CMP1 $0 Compare Register 1

TMRC0_CMP2 $1 Compare Register 2

TMRC0_CAP $2 Capture Register

TMRC0_LOAD $3 Load Register

TMRC0_HOLD $4 Hold Register

TMRC0_CNTR $5 Counter Register

TMRC0_CTRL $6 Control Register

TMRC0_SCR $7 Status and Control Register

TMRC0_CMPLD1 $8 Comparator Load Register 1

TMRC0_CMPLD2 $9 Comparator Load Register 2

TMRC0_COMSCR $A Comparator Status and Control Register

Reserved

TMRC1_CMP1 $10 Compare Register 1

TMRC1_CMP2 $11 Compare Register 2

TMRC1_CAP $12 Capture Register

TMRC1_LOAD $13 Load Register

TMRC1_HOLD $14 Hold Register

TMRC1_CNTR $15 Counter Register

TMRC1_CTRL $16 Control Register

TMRC1_SCR $17 Status and Control Register

TMRC1_CMPLD1 $18 Comparator Load Register 1

TMRC1_CMPLD2 $19 Comparator Load Register 2

TMRC1_COMSCR $1A Comparator Status and Control Register

Reserved

Table 4-12 Quad Timer B Registers Address Map (Continued)

(TMRB_BASE = $00 F080)

Quad Timer B is NOT available in the 56F8165 device