Datasheet

56F8365 Technical Data, Rev. 9

58 Freescale Semiconductor

Table 4-17 Quadrature Decoder 0 Registers Address Map

(DEC0_BASE = $00 F180)

DEC0_DECCR $0 Decoder Control Register

DEC0_FIR $1 Filter Interval Register

DEC0_WTR $2 Watchdog Time-out Register

DEC0_POSD $3 Position Difference Counter Register

DEC0_POSDH $4 Position Difference Counter Hold Register

DEC0_REV $5 Revolution Counter Register

DEC0_REVH $6 Revolution Hold Register

DEC0_UPOS $7 Upper Position Counter Register

DEC0_LPOS $8 Lower Position Counter Register

DEC0_UPOSH $9 Upper Position Hold Register

DEC0_LPOSH $A Lower Position Hold Register

DEC0_UIR $B Upper Initialization Register

DEC0_LIR $C Lower Initialization Register

DEC0_IMR $D Input Monitor Register

Table 4-18 Quadrature Decoder 1 Registers Address Map

(DEC1_BASE = $00 F190)

Quadrature Decoder 1 is NOT available in the 56F8165 device

DEC1_DECCR $0 Decoder Control Register

DEC1_FIR $1 Filter Interval Register

DEC1_WTR $2 Watchdog Time-out Register

DEC1_POSD $3 Position Difference Counter Register

DEC1_POSDH $4 Position Difference Counter Hold Register

DEC1_REV $5 Revolution Counter Register

DEC1_REVH $6 Revolution Hold Register

DEC1_UPOS $7 Upper Position Counter Register

DEC1_LPOS $8 Lower Position Counter Register

DEC1_UPOSH $9 Upper Position Hold Register

DEC1_LPOSH $A Lower Position Hold Register

DEC1_UIR $B Upper Initialization Register

DEC1_LIR $C Lower Initialization Register